Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
RECONF, VLD |
2024-01-29 10:55 |
Kanagawa |
AIRBIC Meeting Room 1-4 (Primary: On-site, Secondary: Online) |
Suppression of output bit width growth in AFE stochastic computing units Daiki Seto, Naoki Fujieda (Aichi Inst. Tech.) VLD2023-81 RECONF2023-84 |
Stochastic Computing (SC) is expected to be applied to fields such as image processing and machine learning. Amplitude a... [more] |
VLD2023-81 RECONF2023-84 pp.7-12 |
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] |
2021-03-26 09:40 |
Online |
Online |
Prototyping of A Packet Aggregation/Disaggregation Router with FPGA Shiro Takayama, Naoki Fujieda, Michihiro Aoki (Aichi Inst. of Tech.) CPSY2020-58 DC2020-88 |
Network traffic volume is increasing due to the growth of IoT services. In particular, increase of short packets may aff... [more] |
CPSY2020-58 DC2020-88 pp.49-54 |
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] |
2019-01-31 14:00 |
Kanagawa |
Raiosha, Hiyoshi Campus, Keio University |
Preliminary evaluation of special instruction implementation methods by high level synthesis Ryodai Iwamoto, Naoki Fujieda, Shuichi Ichikawa, Joji Sakamoto (TUT) VLD2018-88 CPSY2018-98 RECONF2018-62 |
Protection of intellectual properties and technical know-how is an important issue.In our previous work, we proposed imp... [more] |
VLD2018-88 CPSY2018-98 RECONF2018-62 pp.101-106 |
CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] |
2017-01-24 13:55 |
Kanagawa |
Hiyoshi Campus, Keio Univ. |
Expression of Positional registers for Tamper resistance Kiyohiro Sato, Naoki Fujieda, Shuichi Ichikawa (TUT) VLD2016-86 CPSY2016-122 RECONF2016-67 |
[more] |
VLD2016-86 CPSY2016-122 RECONF2016-67 pp.109-114 |
RECONF, CPSY, VLD, IPSJ-SLDM [detail] |
2015-01-30 15:15 |
Kanagawa |
Hiyoshi Campus, Keio University |
MieruSys Project : Developing an Advanced Computer System with Multiple FPGAs Yuki Matsuda, Eri Ogawa, Tomohiro Misono (Tokyo Tech), Naoki Fujieda, Shuichi Ichikawa (TUT), Kenji Kise (Tokyo Tech) VLD2014-146 CPSY2014-155 RECONF2014-79 |
This paper describes the design and current development of MieruSys project which develops a future computer system with... [more] |
VLD2014-146 CPSY2014-155 RECONF2014-79 pp.211-216 |
RECONF, CPSY, VLD, IPSJ-SLDM [detail] |
2015-01-30 15:55 |
Kanagawa |
Hiyoshi Campus, Keio University |
Obfuscated Hardware Implementation of PLC Instructions with Opaque Predicates Kazuki Uyama, Naoki Fujieda, Shuichi Ichikawa (Toyohashi Tech.) VLD2014-148 CPSY2014-157 RECONF2014-81 |
Tamper-proofing technology for instruction sequences of programmable logic controllers(PLCs)is required to protect trade... [more] |
VLD2014-148 CPSY2014-157 RECONF2014-81 pp.221-226 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 09:25 |
Fukuoka |
Centennial Hall Kyushu University School of Medicine |
Rethinking virtual channel usage in network-on-chip Ryosuke Sasakawa, Naoki Fujieda, Shinya Takamaeda-Yamazaki, Kenji Kise (Tokyo Tech) CPSY2012-51 |
An important requirement of routing algorithm is the freedom from deadlock in Network-on-Chip (NoC).For generating deadl... [more] |
CPSY2012-51 pp.21-26 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 09:50 |
Fukuoka |
Centennial Hall Kyushu University School of Medicine |
Network Performance of Multifunction On-chip Router Architectures Shinya Takamaeda-Yamazaki, Naoki Fujieda, Kenji Kise (Tokyo Inst. of Tech.) CPSY2012-52 |
In order to improve the chip-level dependability, we have proposed SmartCore system, NoC-based DMR (Dual Modular Redunda... [more] |
CPSY2012-52 pp.27-32 |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-18 16:25 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Implementation and Evaluation of a Fast and Handy LCD Module Using an FPGA Naoki Fujieda, Kenji Kise (Tokyo Tech) VLD2010-113 CPSY2010-68 RECONF2010-82 |
To output results of, or to debug, embedded systems, display modules which is easy to connect and shows much information... [more] |
VLD2010-113 CPSY2010-68 RECONF2010-82 pp.193-198 |
ICD, IPSJ-ARC, IPSJ-EMB |
2009-01-14 16:00 |
Osaka |
Shoushin Kaikan |
The Cache-Core optimization on Multi-CoreProcessors considering several overheads Yosuke Mori, Akira Moriya, Naoki Fujieda, Kenji Kise (Tokyo Inst. of Tech.) |
The number of cores in a processor increases.
If several cores access to the main memory at the same time, the
memory... [more] |
ICD2008-147 pp.105-110 |
AI |
2006-03-07 14:30 |
Osaka |
Kwansei Gakuin University |
Question Answering System Based on Frequent Words in Web Documents Naoki Fujieda, Koji Iwanuma, Hidetomo Nabeshima (Yamanashi Univ.) |
[more] |
AI2005-51 pp.25-29 |