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Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF, VLD 2024-01-30
14:25		 Kanagawa AIRBIC Meeting Room 1-4
(Primary: On-site, Secondary: Online)		 Exploration of Acceleration of FPGA-based Linear Equation Solver using Approximate Division in Electronic Circuit Simulator
Naoki Kakine, Shuto Yuya, Tetsuo Hironaka, Atsushi Kubota (HCU) VLD2023-96 RECONF2023-99		 (To be available after the conference date) [more] VLD2023-96 RECONF2023-99
pp.93-98
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2023-11-16
13:45		 Kumamoto Civic Auditorium Sears Home Yume Hall
(Primary: On-site, Secondary: Online)		 A Proposal for Acceleration of FPGA-based Linear Equation Solver using Speculative Execution System
Naoki Kakine, Shuto Yuya, Atsushi Kubota, Tetsuo Hironaka (HCU) VLD2023-53 ICD2023-61 DC2023-60 RECONF2023-56		 (To be available after the conference date) [more] VLD2023-53 ICD2023-61 DC2023-60 RECONF2023-56
pp.119-124
RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] 2022-01-25
16:00		 Online Online Design of a Quadruple Precision Floating-Point Arithmetic Unit for FPGAs and its Evaluation by Conjugate Gradient Method
Naoki Kakine, Atsushi Kubota, Tetsuo Hironaka (Hiroshima City Univ) VLD2021-73 CPSY2021-42 RECONF2021-81		 (To be available after the conference date) [more] VLD2021-73 CPSY2021-42 RECONF2021-81
pp.138-142
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