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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 7 of 7  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
Ehime Ehime Prefecture Gender Equality Center
(Primary: On-site, Secondary: Online)
Evaluation of Improvement Plans to Increase the Efficiency of Performance Data Transfer for Server Systems
Chika Iiyama (Ocha Univ.), Akira Hirai, Mari Yamaoka, Naoto Fukumoto (Fujitsu), Masato Oguchi (Ocha Univ.) NS2023-117
In recent years, demand for shared use of multiple servers has been increasing. In order to perform load balancing on th... [more] NS2023-117
CPSY, DC, IPSJ-ARC [detail] 2023-08-04
Hokkaido Hakodate Arena
(Primary: On-site, Secondary: Online)
Parallelization improvements in MPS simulation using Qiskit
Daniel Rodriguez, Takumi Honda, Masafumi Yamazaki, Takanori Nakao, Akihiko Kasagi, Naoto Fukumoto (Fujitsu LTD.) CPSY2023-18 DC2023-18
Tensor Networks, specifically Matrix Product State (MPS), are widely used for quantum circuit simulation due to their be... [more] CPSY2023-18 DC2023-18
CPSY, DC, IPSJ-ARC [detail] 2022-10-12
Niigata Yuzawa Toei Hotel
(Primary: On-site, Secondary: Online)
Performance Evaluation on MPI Communication Using Lossy Compression
Yao Hu (NII), Takumi Honda, Yusuke Nagasaka, Naoto Fukumoto (FUJITSU), Michihiro Koibuchi (NII) CPSY2022-25 DC2022-25
(To be available after the conference date) [more] CPSY2022-25 DC2022-25
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2022-03-11
Online Online Performance Evaluation on Auto Tuned MPI Communication
Yao Hu, Shoichi Hirasawa (NII), Takumi Honda, Yusuke Nagasaka, Naoto Fukumoto (FUJITSU), Michihiro Koibuchi (NII) CPSY2021-61 DC2021-95
In parallel applications, a significant amount of execution time is spent on exchanging data between processes. MPI (Mes... [more] CPSY2021-61 DC2021-95
ICD, IPSJ-ARC 2008-05-14
Tokyo   Performance Balancing: An Efficient Helper-Thread Execution on CMPs
Kenichi Imazato, Naoto Fukumoto, Koji Inoue, Kazuaki Murakami (Kyushu Univ.)
Conventional CMPs attempt to exploit the thread-level parallelism (TLP)
by using all of the cores integrated in a chip.... [more]
ICD, IPSJ-ARC 2008-05-14
Tokyo   Performance Balancing: An Implementation of Efficient On-chip Memory Hierarchy on Cell/B.E.
Tetsuo Hayashi, Naoto Fukumoto, Kenichi Imazato, Koji Inoue, Kazuaki Murakami (Kyushu Univ.)
We have proposed the concept of Performance Balancing to improve the CMP performance. This approach attempts to exploit ... [more] ICD2008-36
ICD, IPSJ-ARC 2007-05-31
Kanagawa   Effect of Data Prefetching on Chip MultiProcessor
Naoto Fukumoto, Tomonobu Mihara, Koji Inoue, Kazuaki Murakami (Kyushu Univ.)
Chip MultiProcessors (or CMPs) can achieve higher performance by means of exploiting thread level parallelism. Increasin... [more] ICD2007-20
 Results 1 - 7 of 7  /   
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