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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CS, IE (Joint) |
2024-12-12 17:05 |
Ehime | Matsuyama City Hall (Ehime, Online) (Primary: On-site, Secondary: Online) |
Characteristic Evaluation of Nonlinear Amplifiers in Semantic Communication for Image Transmission Qijian Zhang, Daisuke Umehara, Nobukazu Takai (KIT)  CS2024-72 |
Recently, with the increase in communication terminals and IoT devices, Deep Joint Source-Channel Coding (Deep JSCC), wh... [more] | CS2024-72 pp.27-32 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2024-11-13 09:00 |
Oita | COMPAL HALL (Oita, Online) (Primary: On-site, Secondary: Online) |
LDO sizing using Bayesian optimization handling PVT corner and requirement Tsuyoshi Masubuchi (GU), Nobukazu Takai (KIT) VLD2024-45 ICD2024-63 DC2024-67 RECONF2024-75 |
In analog integrated circuit design, there is always a risk of redesign. The probability of unexpected design rework can... [more] | VLD2024-45 ICD2024-63 DC2024-67 RECONF2024-75 pp.105-108 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2024-11-13 09:25 |
Oita | COMPAL HALL (Oita, Online) (Primary: On-site, Secondary: Online) |
Comparison of Analog Circuit Sizing Performance in Bayesian Optimization using Algorithms for Higher Dimensions Ryo Takagi (KIT), Tsuyoshi Masubuchi (Gunma Univ.), Yuto Moriguchi, Nobukazu Takai (KIT) VLD2024-46 ICD2024-64 DC2024-68 RECONF2024-76 |
This study focuses on the importance of selecting the appropriate Bayesian optimization algorithm for analog circuit des... [more] | VLD2024-46 ICD2024-64 DC2024-68 RECONF2024-76 pp.109-113 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2024-11-13 09:50 |
Oita | COMPAL HALL (Oita, Online) (Primary: On-site, Secondary: Online) |
Enhancing the Efficiency of Analog Integrated Circuits using by Explainable AI Takayoshi Namura, Yuto Moriguchi, Nobukazu Takai (KIT) VLD2024-47 ICD2024-65 DC2024-69 RECONF2024-77 |
To meet the rapidly increasing demand for analog integrated circuits, automated design techniques are required. However... [more] |
VLD2024-47 ICD2024-65 DC2024-69 RECONF2024-77 pp.114-119 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2024-11-13 10:30 |
Oita | COMPAL HALL (Oita, Online) (Primary: On-site, Secondary: Online) |
Prametric Yield Estimation using Bayesian Neural Networks Yuto Moriguchi, Nobukazu Takai (KIT) VLD2024-51 ICD2024-69 DC2024-73 RECONF2024-81 |
The automation of analog circuit design using machine learning techniques such as reinforcement learning and black-box o... [more] | VLD2024-51 ICD2024-69 DC2024-73 RECONF2024-81 pp.137-141 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2024-11-13 10:55 |
Oita | COMPAL HALL (Oita, Online) (Primary: On-site, Secondary: Online) |
Digital Circuit Topology Search Using Genetic Algorithm with Block Structure Hikaru Horikawa, Nobukazu Takai (KIT) VLD2024-52 ICD2024-70 DC2024-74 RECONF2024-82 |
As the limit is approaching for achieving high performance by transistor miniaturization, research is being conducted to... [more] | VLD2024-52 ICD2024-70 DC2024-74 RECONF2024-82 pp.142-146 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2024-11-13 17:05 |
Oita | COMPAL HALL (Oita, Online) (Primary: On-site, Secondary: Online) |
A development of Adaptive Bias Attachment for Low-Power Analog Circuit Design Shunsuke Akahoshi, Nobukazu Takai (KIT) VLD2024-60 ICD2024-78 DC2024-82 RECONF2024-90 |
This report proposes a circuit that reduces standby power by converting the operating frequency of the circuit to Hi/Lo ... [more] | VLD2024-60 ICD2024-78 DC2024-82 RECONF2024-90 pp.188-192 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2024-11-13 17:30 |
Oita | COMPAL HALL (Oita, Online) (Primary: On-site, Secondary: Online) |
Effects of Input Signal Power on Nonlinear Amplifiers in Semantic Communication Qijian Zhang, Daisuke Umehara, Nobukazu Takai (KIT) VLD2024-61 ICD2024-79 DC2024-83 RECONF2024-91 |
In recent years, the increase in communication traffic in wireless communication has necessitated more efficient data tr... [more] | VLD2024-61 ICD2024-79 DC2024-83 RECONF2024-91 pp.193-197 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-16 15:55 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Kumamoto, Online) (Primary: On-site, Secondary: Online) |
Calculation of Isomorphic/Similar Topology using Graph Theory Yuto Moriguchi, Nobukazu Takai (KIT) VLD2023-55 ICD2023-63 DC2023-62 RECONF2023-58 |
In an automatic integrated circuit design, huge number of circuits are generated and simulated, so the efficiency of cir... [more] | VLD2023-55 ICD2023-63 DC2023-62 RECONF2023-58 pp.131-135 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-16 16:20 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Kumamoto, Online) (Primary: On-site, Secondary: Online) |
A multi bit PWM-DAC with calibration for quantum computing Shunsuke Akahosh, Nobukazu Takai (KIT) VLD2023-56 ICD2023-64 DC2023-63 RECONF2023-59 |
We propose a structure and control method of a multi-bit PWMDAC for controlling qubits operating in a dilution refrigera... [more] | VLD2023-56 ICD2023-64 DC2023-63 RECONF2023-59 pp.136-139 |
| ICD, CPM, ED, EID, EMD, MRIS, OME, SCE, SDM, QIT (Joint) [detail] |
2017-01-31 14:10 |
Hiroshima | Miyajima-Morino-Yado(Hiroshima) (Hiroshima) | Automatic Design of Operational Amplifier Based on Equation-Based and Genetic Algorithm Kento Suzuki, Nobukazu Takai, Yoshiki Sugawara, Satoshi Yoshizawa, Kazuto Okochi, Tsukasa Ishii, Saki Shinoda, Masafumi Fukuda (Gunma Univ.) EMD2016-83 MR2016-55 SCE2016-61 EID2016-62 ED2016-126 CPM2016-127 SDM2016-126 ICD2016-114 OME2016-95 |
It is difficult to design optimal analog circuit in a short time in terms of designing flexibility because the electrica... [more] | EMD2016-83 MR2016-55 SCE2016-61 EID2016-62 ED2016-126 CPM2016-127 SDM2016-126 ICD2016-114 OME2016-95 pp.69-74 |
| ICD, CPM, ED, EID, EMD, MRIS, OME, SCE, SDM, QIT (Joint) [detail] |
2017-01-31 14:35 |
Hiroshima | Miyajima-Morino-Yado(Hiroshima) (Hiroshima) | Automatic Design of Operational Amplifier Using Learning Algorithm Based on Visualization of Variation on Circuit Performance Yoshiki Sugawara, Nobukazu Takai, Kento Suzuki, Satoshi Yoshizawa, Kazuto Okochi, Tsukasa Ishii, Saki Shinoda, Masafumi Fukuda (Gunma Univ.) EMD2016-84 MR2016-56 SCE2016-62 EID2016-63 ED2016-127 CPM2016-128 SDM2016-127 ICD2016-115 OME2016-96 |
[more] | EMD2016-84 MR2016-56 SCE2016-62 EID2016-63 ED2016-127 CPM2016-128 SDM2016-127 ICD2016-115 OME2016-96 pp.75-79 |
| CAS, ICTSSL | 2017-01-26 16:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Tokyo) | Examination of two-phase DC-DC Boost Converter with ZVS-PWM Control Yoshiki Sunaga, Koyo Asaishi, Nobukazu Tsukiji, Natsuko Miki, Syotaro Sakurai, Manimel wadu Sahan dukara, Yasunori Kobori, Nobukazu Takai, Haruo Kobayashi (Gunma Univ.) CAS2016-93 ICTSSL2016-47 |
[more] | CAS2016-93 ICTSSL2016-47 pp.77-80 |
| ICD, CPSY | 2016-12-16 09:40 |
Tokyo | Tokyo Institute of Technology (Tokyo) | Automatic Design of Bias Circuit Based on the Results of Characterized MOSFET Kento Suzuki, Nobukazu Takai, Yoshiki Sugawara, Kazuto Okochi, Satoshi Yoshizawa, Tsukasa Ishii, Saki Shinoda, Masafumi Fukuda (Gunma Univ.) ICD2016-91 CPSY2016-97 |
It is difficult to design optimal analog circuit in a short time in terms of designing flexibility. In an analog circuit... [more] | ICD2016-91 CPSY2016-97 pp.119-122 |
| ICD, CPSY | 2016-12-16 10:05 |
Tokyo | Tokyo Institute of Technology (Tokyo) | Automatic Design of Operational Amplifier Based on Design Information Management System Yoshiki Sugawara, Nobukazu Takai, Kento Suzuki, Kazuto Okochi, Satoshi Yoshizawa, Tsukasa Ishii, Saki Shinoda, Masafumi Fukuda (Gunma Univ.) ICD2016-92 CPSY2016-98 |
Designing optimal analog circuit is difficult in terms of designing flexibility. However, the demand of high performance... [more] | ICD2016-92 CPSY2016-98 pp.123-128 |
| ICD, CPSY | 2016-12-16 15:45 |
Tokyo | Tokyo Institute of Technology (Tokyo) | EMI reduction for hysteretic controlled DC-DC Converter using Pseudo Analog Signal Natsuko Miki, Nobukazu Takai (Gunma Univ.), Yasunori Kobori (Oyama NIT), Koyo Asaishi, nobukazu tsukiji, Yoshiki Sunaga, haruo kobayashi (Gunma Univ.) ICD2016-98 CPSY2016-104 |
In this paper, we propose a circuit implementation of the proposed circuit in EMI reduction of hysteresis control type b... [more] | ICD2016-98 CPSY2016-104 pp.151-154 |
| EE | 2016-02-26 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Tokyo) | Optimum Value of Leakage Inductance For High Efficiency of Current Resonant Converter Naoya Shiraishi (Gunma Univ.), Masashi Ochiai (SANKEN ELECTRIC CO., LTD.), Nobukazu Tsukiji, Shunichiro Todoroki (Gunma Univ.), Yasunori Kobori (Oyama Col.), Haruo Kobayashi, Nobukazu Takai (Gunma Univ.) EE2015-30 |
This paper describes a design issue of the ratio between the leakage inductance and the self-inductance to achieve the ... [more] | EE2015-30 pp.1-6 |
| EE | 2016-02-26 13:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Tokyo) | Implementation and Evaluation of Single-Inductor Dual-Output DC-DC Boost Converter with ZVS-PWM Control Yoshiki Sunaga, Naoya Shiraishi, Koyo Asaishi, Nobukazu Tsukiji, Yasunori Kobori, Nobukazu Takai, Haruo Kobayashi (Gunma Univ.) EE2015-31 |
A Single-Inductor Multi-Output (SIMO) DC-DC converter can generate various supply voltages with one inductor which can r... [more] | EE2015-31 pp.7-12 |
| EMCJ, IEE-EMC, IEE-MAG | 2015-06-25 10:10 |
Overseas | KMITL, Thailand (Overseas) | EMI Reduction by Extended Spread Spectrum in Switching Converter Yasunori Kobori (NIT, Oyama College/Gunma Univ.), Nobukazu Tsukiji, Nobukazu Takai, Haruo Kobayashi (Gunma Univ.) EMCJ2015-18 |
This paper proposes new EMI reduction method by extended spread spectrum using the PLL circuit with pseudo analog noise ... [more] | EMCJ2015-18 pp.1-6 |
| EMCJ, WPT (Joint) |
2015-01-23 09:25 |
Okinawa | Okinawaken Ｊichikaikan (Okinawa) | EMI Reduction for Switching Converter with Analog Spread Spectrum Yasunori Kobori, Shinya Ochiai (NIT, Oyama College), Kotaro Kaneya, Nobukazu Tsukiji, Nobukazu Takai, Haruo Kobayashi (Gunma Univ.) EMCJ2014-93 |
[more] | EMCJ2014-93 pp.45-50 |
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