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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD 2005-04-15
13:00
Fukuoka   A 1.5-ns Access-Time 0.25-μm CMOS/SIMOX SRAM Macrocell -- High Speed and Low-Power Operation by Using Dual-Wordline Scheme --
Nobutaro Shibata, Takako Ishihara (NTT), Shigehiro Kurita, Hideomi Okiyama (NEL)
This paper presents high speed and low-power circuit techniques for small size SRAMs (e.g., on-chip cache memories). Rea... [more] ICD2005-16
pp.19-24
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