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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2014-04-18 11:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit Keiichi Kushida, Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Atsushi Kawasumi, Azuma Suzuki, Yusuke Niki, Miyako Shizuno, Sinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa (Toshiba)  ICD2014-13 |
This paper presents a dual-power-supply SRAM that reduces active and stand-by power from room temperature (RT) to high t... [more] | ICD2014-13 pp.65-70 |
| ICD | 2013-04-12 13:30 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | [Invited Talk]
A Sense-Amplifier-Timing-Generating Circuit Utilizing a Statistical Method for Ultra Low Voltage SRAMs Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Sinichi Sasaki, Tomoaki Yabe (Toshiba) ICD2013-18 |
A variation tolerant sense amplifier timing generator which utilizes a statistical method is proposed. The circuit monit... [more] | ICD2013-18 pp.91-96 |
| ICD | 2013-04-12 14:20 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | [Invited Lecture]
A Power-Reduction Scheme for Dual-Power-Supply SRAM Using BL Power Calculator and Digital LDO Miyako Shizuno, Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Sinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa (Toshiba) ICD2013-19 |
This paper presents a dual-power-supply SRAM that reduces active and stand-by power from room temperature (RT) to high t... [more] | ICD2013-19 pp.97-102 |
| ICD | 2011-04-19 09:55 |
Hyogo | Kobe University Takigawa Memorial Hall | A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yuki Fujimura, Tomoaki Yabe (Toshiba) ICD2011-9 |
A digitized replica bitline delay technique has been proposed for random-variation-tolerant timing generation of static ... [more] | ICD2011-9 pp.49-54 |
| ICD | 2010-04-22 09:00 |
Kanagawa | Shonan Institute of Tech. | [Invited Talk]
A Configurable SRAM with Constant-Negative-Level Write Buffer for Low Voltage Operation with 0.149μm2 Cell in 32nm High-k Metal Gate CMOS Yuki Fujimura, Osamu Hirabayashi, Takahiko Sasaki, Azuma Suzuki, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Gou Fukano, Akira Katayama, Yusuke Niki, Tomoaki Yabe (Toshiba Corp.) ICD2010-1 |
This paper presents a configurable SRAM for low voltage operation with Constant-Negative-Level Write Buffer (CNL-WB) and... [more] | ICD2010-1 pp.1-6 |
| ICD | 2009-04-14 10:15 |
Miyagi | Daikanso (Matsushima, Miyagi) | A Process-Variation-Tolerant Dual-Power-Supply SRAM with 0.179μm2 Cell in 40nm CMOS Using Level-Programmable Wordline Driver Yuki Fujimura, Osamu Hirabayashi, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Keiichi Kushida, Takahiko Sasaki, Akira Katayama, Gou Fukano, Takaaki Nakazato, Yasushi Shizuki, Natsuki Kushiyama, Tomoaki Yabe (Toshiba Co.) ICD2009-5 |
We present a dual-power-supply SRAM with 0.179$\mu$m2 cell in 40nm CMOS, which is 10% smaller than the SRAM scaling tren... [more] | ICD2009-5 pp.21-26 |
| ICD | 2008-04-17 09:25 |
Tokyo | [Invited Talk]
A Single-Power-Supply 0.7V 1GHz 45nm SRAM with an Asymmetrical Unit β-ratio Memory Cell Takahiko Sasaki, Atsushi Kawasumi, Tomoaki Yabe, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida (Toshiba Corp.), Akihito Tohata (Toshiba Microelectronics Corp.), Akira Katayama, Gou Fukano, Yuki Fujimura, Nobuaki Otsuka (Toshiba Corp.) ICD2008-1 |
A single-power supply $64kB$ SRAM is fabricated in a $45nm$ bulk CMOS technology. The SRAM operates at $1GHz$ with a $0.... [more] | ICD2008-1 pp.1-6 |
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| SIP, ICD, IE, IPSJ-SLDM | 2005-10-20 15:50 |
Miyagi | Ichinobo, Sakunami-Spa | DFT Technique for Memory Macro with Built-in ECC Keiichi Kushida, Nobuaki Otsuka, Osamu Hirabayashi, Yasuhisa Takeyama (Toshiba Co.) |
DFT techniques to implement ECC circuitry on memory macro with no additional test cost are proposed. New methodology t... [more] |
SIP2005-111 ICD2005-130 IE2005-75 pp.95-100 |
| ICD, SDM | 2005-08-18 15:45 |
Hokkaido | HAKODATE KOKUSAI HOTEL | A Low Leakage SRAM Macro with Replica Cell Biasing Scheme Osamu Hirabayashi, Yasuhisa Takeyama, Hiroyuki Otake, Keiichi Kushida, Nobuaki Otsuka (Toshiba Corp.) |
(Advance abstract in Japanese is available) [more] | SDM2005-141 ICD2005-80 pp.79-84 |
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