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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 7 of 7  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS, VLD 2023-03-03
11:50		 Okinawa
(Primary: On-site, Secondary: Online)		 A Seed Selection Method to Minimize Test Application Time for Logic BIST Using Pseudo Boolean Optimization
Rei Miura, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.) VLD2022-105 HWS2022-76		  [more] VLD2022-105 HWS2022-76
pp.173-178
HWS, VLD 2023-03-03
13:50		 Okinawa
(Primary: On-site, Secondary: Online)		 A Logic Locking Method based on Function Modification Circuit
Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Rei Miura, Toshinori Hosokawa (Nihon Univ.) VLD2022-107 HWS2022-78		 In recent years, with the increase of VLSI integration, semiconductor design companies to design a VLSI have tended to u... [more] VLD2022-107 HWS2022-78
pp.185-190
DC 2023-02-28
15:15		 Tokyo Kikai-Shinko-Kaikan Bldg
(Primary: On-site, Secondary: Online)		 A Seed Generation Method for Multiple Random Pattern Resistant Transition Faults for BIST
Yangling Xu, Rei Miura, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (KSU) DC2022-89		 With shrinking feature sizes, growing clock frequencies, and decreasing power supply voltage, modern very large integrat... [more] DC2022-89
pp.39-44
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2022-11-29
10:05		 Kumamoto  
(Primary: On-site, Secondary: Online)		 A Seed Generation Method for Multiple Random Pattern Resistant Stuck-at Faults in Built-In Self-Test
Rei Miura, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.) VLD2022-27 ICD2022-44 DC2022-43 RECONF2022-50		  [more] VLD2022-27 ICD2022-44 DC2022-43 RECONF2022-50
pp.49-54
CPSY, DC, IPSJ-ARC [detail] 2022-07-27
09:45		 Yamaguchi Kaikyo Messe Shimonoseki
(Primary: On-site, Secondary: Online)
Enrei Jo, Rei Miura, Toshinori Hosokawa (Nihon Univ), Masayosi Yoshimura (KSU) CPSY2022-1 DC2022-1		 In recent years, with the low power design of VLSIs, many low power oriented don't care (X) identification methods and X... [more] CPSY2022-1 DC2022-1
pp.1-6
CPSY, DC, IPSJ-ARC [detail] 2022-07-27
10:15		 Yamaguchi Kaikyo Messe Shimonoseki
(Primary: On-site, Secondary: Online)		 Faster low-power oriented test generation methods using fault excitation conditions
Rei Miura, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.), Masayuki Arai (Nihon Univ.) CPSY2022-2 DC2022-2		  [more] CPSY2022-2 DC2022-2
pp.7-12
DC 2021-12-10
13:00		 Kagawa
(Primary: On-site, Secondary: Online)		 A Low Power Oriented Multiple Target Test Generation Method
Rei Miura, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.), Masayuki Arai (Nihon Univ.) DC2021-55		 In recent years, since capture power consumption for VLSIs significantly increases in at-speed scan testing, low capture... [more] DC2021-55
pp.1-6
 Results 1 - 7 of 7  /   
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