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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, RECONF 2025-01-16
09:50		 Kanagawa Yokohama Technology Campus Flagship Building (Kanagawa, Online)
(Primary: On-site, Secondary: Online)		 Implementation of an Error Correcting Decoder for Surface Code Using Greedy Algorithm on ASIC by RTL and Behavioral Synthesis
Ren Aoyama (KIT), Junichiro Kaodomoto (UTokyo), Kazutoshi Kobayashi (KIT) VLD2024-78 RECONF2024-108		 Quantum computers are expected to address the limitations of performance improvement due to the miniaturization of class... [more] VLD2024-78 RECONF2024-108
pp.13-17
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2023-11-15
15:30		 Kumamoto Civic Auditorium Sears Home Yume Hall (Kumamoto, Online)
(Primary: On-site, Secondary: Online)		 Error Correction Decoder of the Surface Code designed in a 22-nm Bulk Process for Fault Torelant Quantum Computers
Ren Aoyama (KIT), Junichiro Kadomoto (UTokyo), Kazutoshi Kobayashi (KIT) VLD2023-38 ICD2023-46 DC2023-45 RECONF2023-41		 Error correction is mandatory to realize a quantum computer that can perform practical calculations.
Surface codes is... [more]		 VLD2023-38 ICD2023-46 DC2023-45 RECONF2023-41
pp.49-53
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