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Committee Date Time Place Paper Title / Authors Abstract Paper #
CAS, ICTSSL 2017-01-26
15:20		 Tokyo Kikai-Shinko-Kaikan Bldg. Study of Jitter Generator with Digital Control for High-Speed I/O Interface Circuit
Yuki Ozawa, Haruo Kobayashi (Gunma Univ.), Ryoji Shiota (Socionext) CAS2016-91 ICTSSL2016-45		  [more] CAS2016-91 ICTSSL2016-45
pp.69-72
CAS, NLP 2016-10-27
15:25		 Tokyo   Self-Calibration and Trigger Circuit for 2-Step SAR TDC
Takashi Ida, Yuki Ozawa, Richen Jiang, Haruo Kobayashi (Gunma Univ.), Ryoji Shiota (socionext) CAS2016-48 NLP2016-74		 This paper presents a 2-step successive-approximation-register time-to-digital converter (SAR TDC) architecture with its... [more] CAS2016-48 NLP2016-74
pp.55-60
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