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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2023-08-04 14:55 |
Hokkaido | Hakodate Arena (Primary: On-site, Secondary: Online) |
An Elastic FPGA-based Accelerator for Bayesian Network Structure Learning Ryota Miyagi (The Univ. of Tokyo), Ryota Yasudo (Kyoto Univ.), Kentaro Sano (RIKEN), Hideki Takase (The Univ. of Tokyo)  RECONF2023-15 |
A Bayesian network is a powerful model for representing knowledge involving uncertainty within discrete random variables... [more] | RECONF2023-15 pp.7-12 |
| CPSY, DC, IPSJ-ARC [detail] | 2023-08-03 16:25 |
Hokkaido | Hakodate Arena (Primary: On-site, Secondary: Online) |
CPSY2023-16 DC2023-16 |
(To be available after the conference date) [more] | CPSY2023-16 DC2023-16 pp.49-54 |
| CPSY, DC, IPSJ-ARC [detail] | 2023-08-04 16:50 |
Hokkaido | Hakodate Arena (Primary: On-site, Secondary: Online) |
CPSY2023-24 DC2023-24 |
[more] | CPSY2023-24 DC2023-24 pp.94-99 |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2023-03-23 14:55 |
Kagoshima | Amagi Town Disaster Prevention Center (Tokunoshima) (Primary: On-site, Secondary: Online) |
CPSY2022-36 DC2022-95 |
(To be available after the conference date) [more] | CPSY2022-36 DC2022-95 pp.13-18 |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2023-03-24 13:15 |
Kagoshima | Amagi Town Disaster Prevention Center (Tokunoshima) (Primary: On-site, Secondary: Online) |
CPSY2022-46 DC2022-105 |
(To be available after the conference date) [more] | CPSY2022-46 DC2022-105 pp.72-76 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2022-03-10 13:50 |
Online | Online | Implementation of an Application Mapping Tool for a Circuit-Switched Multi-FPGA System Kohei Ito (Keio Univ.), Ryota Yasudo (Kyoto Univ.), Hideharu Amano (Keio Univ.) CPSY2021-48 DC2021-82 |
(To be available after the conference date) [more] | CPSY2021-48 DC2021-82 pp.20-25 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-07 09:00 |
Hiroshima | Satellite Campus Hiroshima | A Scalable Multi-Path Selection Method for High-Throughput Interconnection Networks Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) CPSY2018-38 |
(To be available after the conference date) [more] | CPSY2018-38 pp.11-16 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2018-07-31 16:15 |
Kumamoto | Kumamoto City International Center | Measuring and Understanding Throughput of Routing Algorithms Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) CPSY2018-23 |
(To be available after the conference date) [more] | CPSY2018-23 pp.133-138 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-08 09:00 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | CPSY2017-44 |
The number of computing nodes increases for both on-chip multi-core systems and supercomputers. Therefore, the network l... [more] | CPSY2017-44 pp.23-28 |
| COMP, ISEC | 2016-12-21 15:30 |
Hiroshima | Hiroshima University | Theoretical Model of Interconnection Networks Consisting of Hosts and Switches Ryota Yasudo (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.), Koji Nakano (Hiroshima Univ.) ISEC2016-79 COMP2016-40 |
Designing interconnection networks with low average shortest path length (ASPL) is an important object for researchers o... [more] | ISEC2016-79 COMP2016-40 pp.51-58 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2016-08-10 18:00 |
Nagano | Kissei-Bunka-Hall (Matsumoto) | CPSY2016-39 |
(To be available after the conference date) [more] | CPSY2016-39 pp.281-286 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-20 16:10 |
Kanagawa | Hiyoshi Campus, Keio University | An Efficient NoC with Decentralized Routers Ryota Yasudo, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Tadao Nakamura (Keio Univ.) VLD2015-95 CPSY2015-127 RECONF2015-77 |
(To be available after the conference date) [more] | VLD2015-95 CPSY2015-127 RECONF2015-77 pp.149-154 |
| ICD, CPSY | 2015-12-18 14:55 |
Kyoto | Kyoto Institute of Technology | Topology Optimization of 3D-Stacked Chips under Maxiumum Wire Length Constraint Hiroshi Nakahara, Daichi Fujiki, Seiichi Tade, Ryota Yasudo, Ryuta Kawano, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Koji Nakano (Hiroshima Univ.), Hideharu Amano (Keio Univ.) ICD2015-91 CPSY2015-104 |
(To be available after the conference date) [more] | ICD2015-91 CPSY2015-104 pp.111-116 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2015-08-06 17:30 |
Oita | B-Con Plaza (Beppu) | A Layout Method of High-Radix Topology onto 3D Stacking Chips Hiroshi Nakahara, Ryota Yasudo, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) CPSY2015-43 |
(To be available after the conference date) [more] | CPSY2015-43 pp.275-280 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 09:40 |
Oita | B-ConPlaza | A Distributed Router Architecture using transparent latches for Networks-on-Chip Ryota Yasudo, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Tadao Nakamura (Keio Univ.) CPSY2014-80 |
Technology scaling creates NoC bottlenecks in both energy and delay, so especially wire delays and the power consumptio... [more] |
CPSY2014-80 pp.45-50 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 13:20 |
Kagoshima | NoC routers using the marching memory through type Ryota Yasudo, Takahiro Kagami, Hideharu Amano (Keio Univ.), Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu (Renesas), Tadao Nakamura (Keio Univ.) CPSY2013-71 |
We propose a NoC(Network-on Chip) router using the marching memory through type in order to reduce the power consumption... [more] | CPSY2013-71 pp.71-76 |
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