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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
NC, MBE
(Joint)
2021-03-05
11:20
Online Online Memory Capacity of Sparse-Coding Hopfield model Implemented on Coherent Ising Machine
Ryuta Sasaki, Toru Aonishi (TokyoTech), Kazushi Mimura (Hiroshima City Univ.), Masato Okada (Univ. Tokyo), Yoshihisa Yamamoto (NTT/Stanford Univ.) NC2020-68
The coherent Ising machine (CIM) is being developed as one of the Ising computers for solving combinatorial optimization... [more] NC2020-68
pp.145-150
NC, MBE
(Joint)
2020-03-06
11:10
Tokyo University of Electro Communications
(Cancelled but technical report was issued)
The Analysis of Associative Memory with Discrete Synapses
Ryuta Sasaki, Toru Aonishi (Tokyo Tech) NC2019-108
Recently, as the increasing needs of the development of high-speed Ising computing specific hardware, it has been requir... [more] NC2019-108
pp.187-192
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-04
10:40
Kochi Kochi City Culture-Plaza A Proposal of Message Driven IP Core Interface
Ryuta Sasaki, Tsugio Nakamura, Hiroshi Kasahara, Narito Fuyutsume (Tokyo Denki Univ.) CPSY2009-48
In a ULSI such as SoC, various IP cores developed by different firms are integrated into single-chip. Therefore problems... [more] CPSY2009-48
pp.31-36
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-29
10:55
Kanagawa   A Proposal of Message Driven IP Core Interface
Ryuta Sasaki, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) VLD2008-96 CPSY2008-58 RECONF2008-60
In a ULSI such as SoC, various IP cores with different development firms are integrated in single-chip. Therefore proble... [more] VLD2008-96 CPSY2008-58 RECONF2008-60
pp.31-36
 Results 1 - 4 of 4  /   
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