| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| US | 2016-07-29 13:30 |
Fukuoka | Chikushi Campus, Kyushu University | Fabrication of mesoporous silica via sintering nano-particles Hiroshi Ikeda (kyushu dental univ.), Satoru Akiyama, Shigeru Fujino (Kyushu univ.)  US2016-30 |
[more] | US2016-30 pp.1-2 |
| ICD | 2010-04-22 12:05 |
Kanagawa | Shonan Institute of Tech. | Low-VT CMOS Preamplifier for 0.5-V Gigabit-DRAM Arrays Akira Kotabe, Yoshimitsu Yanagawa, Satoru Akiyama, Tomonori Sekiguchi (Hitachi) ICD2010-6 |
A novel low-VT CMOS preamplifier was developed for low-power and high-speed gigabit DRAM arrays. The sensing time of the... [more] | ICD2010-6 pp.29-33 |
| ICD | 2009-04-13 13:30 |
Miyagi | Daikanso (Matsushima, Miyagi) | [Invited Talk]
Trend in Multi-Gigabit DRAM Technology and Low-Vt Small-Offset Gated Preamplifier for Sub-1-V Arrays Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh (Hitachi, Ltd.,) ICD2009-2 |
[more] | ICD2009-2 pp.7-12 |
| ICD | 2009-04-13 15:40 |
Miyagi | Daikanso (Matsushima, Miyagi) | [Panel Discussion]
Which memory technology win win the low-VDD race in SoC? Hideto Hidaka (Renesas Tech.), Masanao Yamaoka (Hitachi, Ltd.), Shinji Miyano (Toshiba Corp.), Satoru Akiyama (Hitachi, Ltd.), Tadahiko Sugibayashi (NEC), Syoichiro Kawashima (Fujitsu Limited), Masataka Osaka (Panasonic) ICD2009-4 |
A panel discussion session will high-light low-voltage memory trends, limitations, and future prospects by discussing on... [more] | ICD2009-4 p.19 |
| ICD, SDM | 2008-07-17 15:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Fully Logic-Process-Compatible, SESO-memory Cell with 0.1-FIT/Mb Soft Error, 100-MHz Random Cycle, and 100-ms Retention Norifumi Kameshiro, Takao Watanabe, Tomoyuki Ishii, Toshiyuki Mine (Hitachi, Ltd.), Toshiaki Sano (Renesas), Hidefumi Ibe, Satoru Akiyama (Hitachi, Ltd.), Kazumasa Yanagisawa, Takashi Ipposhi, Toshiaki Iwamatsu, Yasuhiko Takahashi (Renesas) SDM2008-136 ICD2008-46 |
We proposed a fully logic compatible process for a single electron shut-off transistor (SESO). A 1-kb memory-cell array ... [more] | SDM2008-136 ICD2008-46 pp.47-52 |
| SIP, ICD, IE, IPSJ-SLDM | 2005-10-20 15:30 |
Miyagi | Ichinobo, Sakunami-Spa | A Memory Controller that Reduces Latency of Cached SDRAM Seiji Miura, Satoru Akiyama (Hitachi,Ltd) |
The proposed controller has two main control schemes, address-alignment control and dummy-cache control scheme. These tw... [more] | SIP2005-110 ICD2005-129 IE2005-74 pp.89-93 |
| ICD, SDM | 2005-08-19 13:50 |
Hokkaido | HAKODATE KOKUSAI HOTEL | A 0.4-V High-Speed Long-Retention-Time DRAM Array with 12 F2 Twin Cell Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa (Hitachi), Kazuhiko Kajigaya (ELPIDA), Takayuki Kawahara (Hitachi) |
We propose and evaluate a DRAM cell array with 12-F2 twin cell in terms of speed, retention time, and low-voltage operat... [more] | SDM2005-152 ICD2005-91 pp.55-60 |
| ICD | 2005-04-14 14:30 |
Fukuoka | [Invited Talk]
Statistical Integration In Multigigabit DRAM Design Tomonori Sekiguchi, Satoru Akiyama (Hitachi), Kazuhiko Kajigaya (Elpida), Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara (Hitachi) |
Concordant memory-array design incorporates device fluctuations statistically into signal-to-noise ratio analysis in DRA... [more] | ICD2005-8 pp.37-42 |
|
[Return to Top Page]