IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 14 of 14  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD 2011-12-15
16:10
Osaka   [Poster Presentation] Sleep Depth Controlling for Run-Time Leakage Power Saving
Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura (Tokyo Univ.) ICD2011-114
Since process technology has been in deep sub-micron era, leakage power dissipation is one of major concerns, and its re... [more] ICD2011-114
p.69
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-11-30
14:15
Fukuoka Kyushu University Accurate Delay Analysis Method of Power-Gated Circuit
Seidai Takeda, Kim Kyundong, Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2010-70 DC2010-37
We present a noble delay computation methodology for cluster-based power-gated circuit. Our scheme can compute circuit d... [more] VLD2010-70 DC2010-37
pp.93-98
VLD 2009-03-13
13:00
Okinawa   Implementation and performance measurement of low-power multiplier applying Run Time Power Gating
Mitsutaka Nakata, Toshiaki Shirai (Shibaura Inst. of Tech.), Seidai Takeda (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2008-162
This paper describes an implementation of low power multiplier applying Run Time Power Gating using 90nm process. Leakag... [more] VLD2008-162
pp.213-218
RECONF 2008-05-23
09:00
Fukushima The University of Aizu Designing And Evaluating Dynamically Reconfigurable Processor with Power Gating Technique
Yoshiki Saito (Keio Univ.), Toshiaki Shirai (Shibaura Inst.), Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi (Keio Univ.), Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami (Shibaura Inst.), Hideharu Amano (Keio Univ.) RECONF2008-10
A dynamically reconfigurable processor achieves high performance making the best use of high degree of parallelism with ... [more] RECONF2008-10
pp.55-60
ICD, IPSJ-ARC 2008-05-14
15:30
Tokyo   A Fine Grain Dynamic Sleep Control Scheme in Superscalar Processor
Yu Kojima, Daisuke Ikebuchi, Naomi Seki, Yohei Hasegawa, Hideharu Amano (Keio Univ.), Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami (Shibaura Inst of Tech), Tetsuya Sunada, Jun Kanai, Mitaro Namiki (Tokyo Univ. of Agri & Tech), Masaaki Kondo, Hiroshi Nakamura (Univ. of Tokyo)
Geyser-0 is a low power MIPS R3000 processor which uses a novel fine grain power gating technique to computational units... [more] ICD2008-33
pp.87-92
VLD, ICD 2008-03-06
10:05
Okinawa TiRuRu Design and Analysis of on-chip leakage monitor using MTCMOS
Satoshi Koyama, Seidai Takeda, Kimiyoshi Usami (S.I.T.) VLD2007-146 ICD2007-169
On cutting-edge semiconductor process, leakage current varies drastically due to process variation and temperature chang... [more] VLD2007-146 ICD2007-169
pp.13-18
RECONF, CPSY, VLD, IPSJ-SLDM 2008-01-16
15:10
Kanagawa Hiyoshi Campus, Keio University Development of verification and power estimation methodology for circuits with Run Time Power Gating
Mitsutaka Nakata, Toshiaki Shirai, Toshihiro Kashima, Seidai Takeda, Kimiyoshi Usami (S.I.T.), Naomi Seki, Yohei Hasegawa, Hideharu Amano (Keio Univ.) VLD2007-111 CPSY2007-54 RECONF2007-57
When applying Run-Time Power Gating (RTPG) to a design,logic verification is one of the major problems.Gate-level simula... [more] VLD2007-111 CPSY2007-54 RECONF2007-57
pp.37-42
RECONF, CPSY, VLD, IPSJ-SLDM 2008-01-16
15:35
Kanagawa Hiyoshi Campus, Keio University Physical design and Evaluation of MIPS R3000 processor applying Run Time Power Gating
Toshiaki Shirai, Toshihiro Kashima, Seidai Takeda, Mitsutaka Nakata, Kimiyoshi Usami (S.I.T.), Yohei Hasegawa, Naomi Seki, Hideharu Amano (Keio Univ.) VLD2007-112 CPSY2007-55 RECONF2007-58
Run Time Power Gating (RTPG) is a technology that reduces leakage power in a temporally/spatially fine-grained manner. T... [more] VLD2007-112 CPSY2007-55 RECONF2007-58
pp.43-48
ICD, SDM 2007-08-23
15:00
Hokkaido Kitami Institute of Technology Power Measurement for a Multiplier with Run Time Power Gating
Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Naoaki Ohkubo, Kimiyoshi Usami (S.I.T) SDM2007-152 ICD2007-80
This paper describes a result of measurement of a Multiplier with Run Time Power Gating (RTPG). This multiplier has a sc... [more] SDM2007-152 ICD2007-80
pp.63-68
ICD, IPSJ-ARC 2007-05-31
16:45
Kanagawa   A fine grain dynamic sleep control scheme in MIPS R3000
Naomi Seki, Yohei Hasegawa, Hideharu Amano (Keio Univ.), Naoaki Ohkubo, Seidai Takeda, Toshihiro Kashima, Toshiaki Shirai, Kimiyoshi Usami (Shibaura Inst. Tech.), Masaaki Kondo, Hiroshi Nakamura (U. of Tokyo)
 [more] ICD2007-25
pp.49-54
RECONF 2007-05-18
09:30
Ishikawa Kanazawa Bunka Hall Power Reduction of Dynamical Reconfigurable Processor MuCCRA
Keiichiro Hirai (Keio Univ.), Seidai Takeda (SIT.), Takashi Nishimura, Youhei Hasegawa, Satoshi Tsutsumi (Keio Univ.), Kimiyoshi Usami (SIT.), Hideharu Amano (Keio Univ.) RECONF2007-11
Although dynamically recon gurable processors have received an attention as a cost-e ective o -load engine for mobile
d... [more]
RECONF2007-11
pp.61-66
ICD, VLD 2007-03-09
15:40
Okinawa Mielparque Okinawa Analysis for factors that affect power dissipation for Multiplier applying Run Time Power Gating
Seidai Takeda, Toshihiro Kashima, Toshiaki Shirai, Naoaki Ohkubo, Kimiyoshi Usami (S.I.T.)
 [more] VLD2006-154 ICD2006-245
pp.81-85
RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2006-11-30
09:25
Fukuoka Kitakyushu International Conference Center Architecture Design for Low-Power Multiplier applying Run Time Power Gating
Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Naoaki Ohkubo, Kimiyoshi Usami (S.I.T)
 [more] VLD2006-73 DC2006-60
pp.7-12
RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2006-11-30
09:50
Fukuoka Kitakyushu International Conference Center Physical Design for Low-Power Multiplier applying Run time Power Gating
Seidai Takeda, Toshihiro Kashima, Toshiaki Shirai, Naoaki Ohkubo, Kimiyoshi Usami (S.I.T.)
 [more] VLD2006-74 DC2006-61
pp.13-18
 Results 1 - 14 of 14  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan