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 Results 1 - 20 of 64  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2022-03-01
10:55
Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)
On Correction for Temperature and Voltage Effects in On-Chip Delay Measurement
Takaaki Kato (KIT), Yousuke Miyake (PRIVATECH), Seiji Kajihara (KIT) DC2021-67
It is effective for aging of a logic circuit to measure a circuit delay periodically in field. In order to compare the d... [more] DC2021-67
pp.18-23
DC 2022-03-01
14:20
Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)
Evaluation of Efficiency for a Method to Locate High Power Consumption with Switching Provability
Ryu Hoshino, Taiki Utsunomiya, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2021-73
In recent years, as the high speed and miniaturization of LSIs have improved, it has become more difficult to test LSIs.... [more] DC2021-73
pp.51-56
DC 2021-02-05
12:00
Online Online Locating High Power Consuming Area in Logic parts Caused by Memory Size and Shapes
Daiki Takafuji, Ryu Hoshino, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2020-72
 [more] DC2020-72
pp.18-23
DC 2020-12-11
13:00
Hyogo
(Primary: On-site, Secondary: Online)
A Degradation Prediction of Circuit Delay Using A Gradient Descent Method
Seiichirou Mori, Masayuki Gondou, Yousuke Miyake, Takaaki Kato, Seiji Kajihara (Kyutech) DC2020-59
As the risk of aging-induced faults of VLSIs is increasing, highly reliable systems require to predict when the aging-in... [more] DC2020-59
pp.1-6
VLD, DC, RECONF, ICD, IPSJ-SLDM
(Joint) [detail]
2020-11-17
10:30
Online Online Power Analysis Based on Probability Calculation of Small Regions in LSI
Ryo Oba, Ryu Hoshino, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) VLD2020-13 ICD2020-33 DC2020-33 RECONF2020-32
Power consumption in LSI testing is higher than in functional mode since more switching activities occur. High power con... [more] VLD2020-13 ICD2020-33 DC2020-33 RECONF2020-32
pp.12-17
DC 2020-02-26
10:00
Tokyo   On Machine Learning Based Accuracy Improvement for A Digital Temperature and Voltage Sensor
Masayuki Gondo, Yousuke Miyake, Seiji Kajihara (Kyutech) DC2019-86
To measure an on-chip temperature and voltage during VLSI operation, an RO(Ring Oscillator)-based digital temperature an... [more] DC2019-86
pp.1-6
DC 2020-02-26
14:35
Tokyo   Power Analysis for Logic Area of LSI Including Memory Area
Yuya Kodama, Kohei Miyase, Daiki Takafuji, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2019-93
Power consumption during LSI testing is higher than functional mode. Excessive IR-drop causes excessive delay, resulting... [more] DC2019-93
pp.43-48
DC 2020-02-26
15:00
Tokyo   Improving Controllability of Signal Transitions in the High Switching Area of LSI
Jie Shi, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2019-94
Power consumption in LSI testing is larger than in functional mode. High power consumption causes excessive IR-drop and ... [more] DC2019-94
pp.49-54
DC 2019-12-20
16:30
Wakayama   Aging Observation using On-Chip Delay Measurement in Long-term Reliability Test
Yousuke Miyake, Takaaki Kato, Seiji Kajihara (Kyutech), Masao Aso, Haruji Futami, Satoshi Matsunaga (Syswave), Yukiya Miura (TMU) DC2019-85
Avoidance of delay-related faults due to aging phenomena is an important issue of VLSI systems. Periodical delay measure... [more] DC2019-85
pp.37-42
DC 2019-02-27
10:15
Tokyo Kikai-Shinko-Kaikan Bldg. Analysis of the hotspot distribution in the LSI
Yudai Kawano, Kohei Miyase (Kyutech), Shyue-Kung Lu (NTUST), Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2018-74
Performance degrading caused by high IR-drop in normal functional mode of LSI can be solved by improving power supply ne... [more] DC2018-74
pp.19-24
DC 2018-12-14
13:00
Okinawa Miyako Seisyonen-No-Ie On-Chip Delay Measurement for In-field Periodic Test of FPGAs
Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT) DC2018-58
Delay-related failures due to aging phenomena are a critical issue of state-of-the-art VLSI systems. In order to detect ... [more] DC2018-58
pp.1-6
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-06
13:25
Hiroshima Satellite Campus Hiroshima Evaluation of Flexible Test Power Control for Logic BIST in TEG Chips
Takaaki Kato (KIT), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (KIT) VLD2018-57 DC2018-43
Scan-based logic BIST has a crucial problem of high test power dissipation. Its solution requires a flexible test power ... [more] VLD2018-57 DC2018-43
pp.125-130
DC 2018-02-20
11:00
Tokyo Kikai-Shinko-Kaikan Bldg. Locating Hot Spots with Justification Techniques in a Layout Design
Yudai Kawano, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen (Kyutech) DC2017-80
In general, power consumption during LSI testing is higher than functional operation. Excessive power consumption in at-... [more] DC2017-80
pp.19-24
DC 2018-02-20
15:05
Tokyo Kikai-Shinko-Kaikan Bldg. A method for improving an estimation accuracy of a specific temperature and voltage range in a digital temperature and voltage sensor
Kenji Inoue, Yousuke Miyake, Seiji Kajihara (Kyutech) DC2017-85
An RO(Ring Oscillator)-based digital temperature and voltage sensor has been proposed in order to measure an on-chip tem... [more] DC2017-85
pp.49-54
DC 2017-12-15
15:30
Akita Akita Study Center, The Open University of Japan A Test Clock Observation Method Using Time-to-Digital Converters for Built-In Self-Test in FPGAs
Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT) DC2017-75
A delay measurement method combining a logic BIST with a variable test clock has been proposed to improve field reliabil... [more] DC2017-75
pp.37-42
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-07
09:00
Kumamoto Kumamoto-Kenminkouryukan Parea Flip-Flop Selection for Multi-Cycle Test with Partial Observation in Scan-Based Logic BIST
Shigeyuki Oshima, Takaaki Kato (Kyutech), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (Kyutech) VLD2017-41 DC2017-47
A logic BIST scheme using multi-cycle test with partial observation has been proposed. In the scheme, the selection of f... [more] VLD2017-41 DC2017-47
pp.85-90
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-07
09:25
Kumamoto Kumamoto-Kenminkouryukan Parea On Avoiding Test Data Corruption by Optimal Scan Chain Grouping
Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara (KIT), Jun Qian (AMD) VLD2017-42 DC2017-48
Scan shift operations cause many gates to switch simultaneously. As a result, excessive IR-drop may occur, disrupting th... [more] VLD2017-42 DC2017-48
pp.91-94
CPSY, DC, IPSJ-ARC
(Joint) [detail]
2017-07-26
16:15
Akita Akita Atorion-Building (Akita) A Two-Temperature-Point Calibration Method for A Digital Temperature And Voltage Sensor
Yousuke Miyake, Yasuo Sato, Seiji kajihara (KIT) DC2017-19
A measurement method of a digital sensor using ring oscillators to measure a temperature and a voltage of a VLSI was pro... [more] DC2017-19
pp.19-24
DC 2017-02-21
10:55
Tokyo Kikai-Shinko-Kaikan Bldg. IR-Drop Analysis on Different Power Supply Network Designs
Kohei Miyase, Kiichi Hamasaki (Kyutech), Matthias Sauer (University of Freiburg), Ilia Polian (University of Passau), Bernd Becker (University of Freiburg), Xiaoqing Wen, Seiji kajihara (Kyutech) DC2016-75
The shrinking feature size and low power design of LSI make LSI testing very difficult. Further development of LSI techn... [more] DC2016-75
pp.7-10
DC 2016-02-17
10:25
Tokyo Kikai-Shinko-Kaikan Bldg. Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation
Fuqiang Li, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara (Kyutech) DC2015-87
Both logic paths and clock paths are subject to the impact of IR-Drop which occurs in capture mode during scan test. Thi... [more] DC2015-87
pp.7-12
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