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Conference Papers (Available on Advance Programs) (Sort by: Date Descending)

Committee	Date Time	Place		Paper Title / Authors	Abstract	Paper #
SR	2024-05-21 15:10	Kagoshima	Yokacenter (Kagoshima) (Primary: On-site, Secondary: Online)	Input Resolution Prediction for Accelerating Deep Learning based Radio Frequency Fingerprinting Kazutoshi Hirose, Seiya Shibata, Taichi Ohtsuji, Takashi Takenaka (NEC)	[more]
VLD	2017-03-02 13:30	Okinawa	Okinawa Seinen Kaikan	[Invited Talk] Accelerating an IoT Application by using CPU-FPGA tightly coupled architecture Yuki Kobayashi, Yoshikazu Watanabe, Seiya Shibata, Takashi Takenaka, Takeo Hosomi, Yuichi Nakamura (NEC) VLD2016-115	CPU-FPGA tightly coupled architecture is an emerging architecture where FPGA is tightly coupled with CPU. We introduce a... [more]	VLD2016-115 p.79
RECONF	2016-09-06 09:10	Toyama	Univ. of Toyama	[Invited Talk] Accelerating an IoT Application by using CPU-FPGA tightly coupled architecture Yuki Kobayashi, Yoshikazu Watanabe, Seiya Shibata, Takashi Takenaka, Takeo Hosomi, Yuichi Nakamura (NEC) RECONF2016-32	CPU-FPGA tightly coupled architecture is an emerging architecture where FPGA is tightly coupled with CPU. We introduce a... [more]	RECONF2016-32 p.37
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail]	2012-11-26 10:30	Fukuoka	Centennial Hall Kyushu University School of Medicine	Automated Identification of Performance Bottleneck on Embedded Systems for Architecture Exploration Yuki Ando (Nagoya Univ.), Seiya Shibata (NEC), Shinya Honda (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.) VLD2012-62 DC2012-28	This paper presents a method to identify performance bottleneck on an embedded systems. At the same time, our method exp... [more]	VLD2012-62 DC2012-28 pp.19-24
RECONF	2012-05-29 16:45	Okinawa	Tiruru (Naha Okinawa, Japan)	Implementation and evaluation of the AES/ADPCM on STP and FPGA with Behavioral Synthesis Yukihito Ishida, Seiya Shibata, Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ) RECONF2012-14	Reconfigurable techniques are attracting attention as an alternative to dedicated hardware of SoC. We have evaluated FP... [more]	RECONF2012-14 pp.77-82
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail]	2011-11-29 09:00	Miyazaki	NewWelCity Miyazaki	Synthesis of efficient data fetch mechanism from the high level communication description Masato Minato, Yuki Ando, Seiya Shibata (Nagoya Univ.), Tomoo Kinoshita (Soliton Systems), Shinya Honda, Hiroaki Takada (Nagoya Univ.) VLD2011-67 DC2011-43	This paper presents efficient data fetch mechanism for the FIFO-based implementation generated by SystemBuilder, a syste... [more]	VLD2011-67 DC2011-43 pp.91-96
RECONF	2011-09-27 09:00	Aichi	Nagoya Univ.	Case Studies on an FPGA with System-Level Multiprocessor Design Toolset Seiya Shibata, Yuki Ando, Shinya Honda (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.) RECONF2011-32	This paper presents a system-level multiprocessor design toolkit: SystemBuilder. SystemBuilder enables system designers... [more]	RECONF2011-32 pp.57-62
DC, CPSY, IPSJ-SLDM, IPSJ-EMB	2008-03-27 09:30	Kagoshima		Function and Efficiency Enhancement of A Simulation Environment with Multiprocessor RTOS Hiroshi Aiba, Seiya Shibata, Takashi Furukawa, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ.) DC2007-86 CPSY2007-82	This paper presents two improvement techniques which we have applied for our multiprocessor simulation environment with ... [more]	DC2007-86 CPSY2007-82 pp.13-18
VLD, ICD	2008-03-06 14:40	Okinawa	TiRuRu	A Case Study on MPEG4 Decoder Design with SystemBuilder Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ.) VLD2007-151 ICD2007-174	This paper presents a case study on designing an MPEG4 decoder system using our system-level design environment named Sy... [more]	VLD2007-151 ICD2007-174 pp.43-48

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