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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 18 of 18  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2022-11-30
15:10
Ishikawa Kanazawa Bunka Hall
(Primary: On-site, Secondary: Online)
FPGA Implementation and Area Evaluation of JTAG Access Mechanism Using Lightweight One-Time Password Authentication Scheme
Hisashi Okamoto, Jun Ma, Senling Wang, Hiroshi Kai, Hiroshi Takahashi (Ehime Univ), Akihiro Shimizu (Kochi Univ. of Technology) VLD2022-48 ICD2022-65 DC2022-64 RECONF2022-71
(To be available after the conference date) [more] VLD2022-48 ICD2022-65 DC2022-64 RECONF2022-71
pp.168-173
DC 2021-02-05
14:25
Online Online Fault Coverage Estimation Method in Multi-Cycle Testing
Norihiro Nakaoka, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas Electronics Corp.) DC2020-75
 [more] DC2020-75
pp.36-41
VLD, DC, RECONF, ICD, IPSJ-SLDM
(Joint) [detail]
2020-11-17
11:20
Online Online Control Point Selection Approach for Scan Pattern Reduction under Multi-cycle Test
Hikaru Tamaki, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas) VLD2020-15 ICD2020-35 DC2020-35 RECONF2020-34
 [more] VLD2020-15 ICD2020-35 DC2020-35 RECONF2020-34
pp.24-29
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-14
16:10
Ehime Ehime Prefecture Gender Equality Center Analysis of Fault Detection Degradation Issue in Multi-cycle Test Scheme using Probabilistic Evaluation Method
Norihiro Nakaoka, Tomoki Aono, Sohshi Kudoh, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas) VLD2019-45 DC2019-69
In order to ensure the functional safety of advanced autonomous driving systems, a power-on self-test
(POST) is require... [more]
VLD2019-45 DC2019-69
pp.145-150
DC 2019-02-27
14:05
Tokyo Kikai-Shinko-Kaikan Bldg. FF Toggle Control Point Selection Methods for Fault Detection Enhancement under Multi-cycle Testing
Tomoki Aono, Hanan T.Al-Awadhi, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas) DC2018-79
Multi-cycle Test is a promising way to reduce the test volume of Logic-BIST (Logic Built-in Self-Test) based POST (Power... [more] DC2018-79
pp.49-54
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-06
13:25
Hiroshima Satellite Campus Hiroshima Evaluation of Flexible Test Power Control for Logic BIST in TEG Chips
Takaaki Kato (KIT), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (KIT) VLD2018-57 DC2018-43
Scan-based logic BIST has a crucial problem of high test power dissipation. Its solution requires a flexible test power ... [more] VLD2018-57 DC2018-43
pp.125-130
DC 2018-02-20
16:10
Tokyo Kikai-Shinko-Kaikan Bldg. Testing the Bridge Interconnect Fault for Memory based Reconfigurable Logic Device (MRLD)
Senling Wang, Tatsuya Ogawa, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Masayuki Sato, Mitsunori Katsu (TRL), Shoichi Sekiguchi (TAIYOYUDEN) DC2017-87
MRLD is a promising alternative to FPGA with the benefits of low production cost, low power and small delay. In order to... [more] DC2017-87
pp.61-66
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-07
09:00
Kumamoto Kumamoto-Kenminkouryukan Parea Flip-Flop Selection for Multi-Cycle Test with Partial Observation in Scan-Based Logic BIST
Shigeyuki Oshima, Takaaki Kato (Kyutech), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (Kyutech) VLD2017-41 DC2017-47
A logic BIST scheme using multi-cycle test with partial observation has been proposed. In the scheme, the selection of f... [more] VLD2017-41 DC2017-47
pp.85-90
DC 2017-02-21
11:35
Tokyo Kikai-Shinko-Kaikan Bldg. Built-In Self Diagnosis Architecture for Logic Design
Keisuke Kagawa, Fumiya Yano, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Satoshi Ohtake (Oita Univ.) DC2016-76
Recently, roles of automotive LSI to realize a functional safety of vehicle are increasing. In order to guarantee the fu... [more] DC2016-76
pp.11-16
DC 2017-02-21
16:35
Tokyo Kikai-Shinko-Kaikan Bldg. Design for Evaluation of TSV based Interconnections in 3D-SIC -- Interconnection Resistance Evaluation with Analog Boundary Scan --
Shuichi Kameyama (Ehime Univ./Fujitsu), Senling Wang, Hiroshi Takahashi (Ehime Univ.) DC2016-83
This paper introduces a concept of Design for Evaluation (DFE) that is a design method to embed circuits for quality eva... [more] DC2016-83
pp.53-58
DC 2016-02-17
15:15
Tokyo Kikai-Shinko-Kaikan Bldg. Analog Circuit Design for a Precision Resistance Measurement of TSVs
Senling Wang, Keisuke Kagawa (Ehime Univ.), Shuichi Kameyama (Fujitsu), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2015-94
 [more] DC2015-94
pp.49-54
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-03
11:40
Nagasaki Nagasaki Kinro Fukushi Kaikan Implementation of Precision Resistance Measurement of TSVs Using Analog Boundary Scan
Senling Wang, Keisuke Kagawa (Ehime Univ.), Shuichi Kameyama (Fujitsu), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) VLD2015-65 DC2015-61
 [more] VLD2015-65 DC2015-61
pp.177-182
DC 2015-02-13
16:25
Tokyo Kikai-Shinko-Kaikan Bldg A Simulated Annealing based Low IR Drop Pattern Selection Method for Resistive Open Fault Diagnosis
Senling Wang, Taiga Inoue, Hanan T.al-awadhi, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2014-87
 [more] DC2014-87
pp.55-60
DC 2014-06-20
14:30
Tokyo Kikai-Shinko-Kaikan Bldg. Capture Power Evaluation for A Low Power BIST Method Using A TEG Chip
Toshiya Nishida (Kyushu Inst. of Tech.), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.) DC2014-13
Voltage drop by a momentary current change during capture cycles in scan-based testing brings an increase in path delay ... [more] DC2014-13
pp.21-26
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-28
14:55
Fukuoka Centennial Hall Kyushu University School of Medicine A Scan-Out Power Reduction Method for Multi-Cycle BIST
Senling Wang, Yasuo Sato, Seiji Kajihara, Kohei Miyase (Kyutech) VLD2012-102 DC2012-68
Excessive power dissipation in logic BIST is a serious problem. Although many low power BIST approaches that focus on sc... [more] VLD2012-102 DC2012-68
pp.249-254
DC 2012-06-22
15:45
Tokyo Room B3-1 Kikai-Shinko-Kaikan Bldg An Evaluation of Low Power BIST Method
Yasuo Sato, Senling Wang, Takaaki Kato, Kohei Miyase, Seiji Kajihara (Kyutech) DC2012-14
Low-power test technology has been investigated deeply to achieve an accurate and efficient testing. Although many sophi... [more] DC2012-14
pp.33-38
DC 2012-02-13
11:55
Tokyo Kikai-Shinko-Kaikan Bldg. A method to reduce shift-toggle rate for low power BIST
Takaaki Kato, Senling Wang, Kohei Miyase, Yasuo Sato, Seiji Kajihara (KIT) DC2011-80
Logic BIST using scan design has a problem with high power dissipation during test. In this work we propose a method tha... [more] DC2011-80
pp.25-29
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-11-29
16:05
Fukuoka Kyushu University Rotating Test and Pattern Partitioning for Field Test
Senling Wang, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen (Kyushu Insti. Tech.)
 [more]
 Results 1 - 18 of 18  /   
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