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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 7 of 7  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM [detail] 2008-11-14
13:50
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] [Invited]Robust Design of Embedded SRAM on Deep-submicron Technology
Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Hirofumi Shinohara (Renesas Technology Corp.) SDM2008-178
We develop high-density SRAM module in deep-submicron CMOS technology with the variation tolerant assist circuits agains... [more] SDM2008-178
pp.55-60
ICD, SDM 2008-07-17
10:30
Tokyo Kikai-Shinko-Kaikan Bldg. A 45 nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations
Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka (Renesas Tech.), Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Katsuji Satomi, Hironori Akamatsu (Matsushita Elec.), Hirofumi Shinohara (Renesas Tech.) SDM2008-131 ICD2008-41
We develop 512 Kb SRAM module in 45 nm LSTP CMOS technology with the variation tolerant assist circuits against process ... [more] SDM2008-131 ICD2008-41
pp.17-22
ICD, SDM 2007-08-24
16:05
Hokkaido Kitami Institute of Technology A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues
Satoshi Ishikura, M. Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi (Matushita Electric Industrial), Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara (Renesas Technology), Hironori Akamatsu (Matushita Electric Industrial) SDM2007-168 ICD2007-96
We propose a new 2port SRAM with a 8T single-read-bitline (SRBL) memory cell for 45nm SOCs. Access time tends to be slow... [more] SDM2007-168 ICD2007-96
pp.145-148
ICD 2007-04-13
09:40
Oita   [Invited Talk] A 65 nm Embedded SRAM with Wafer Level Burn-In Mode, Leak-Bit Redundancy and E-trim Fuse for Known Good Die
Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono (Renesas Technology), Yuji Oda (Shikino High-Tech), Susumu Imaoka (Renesas Design), Keiichi Usui (Daioh Electric), Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) ICD2007-11
We propose a Wafer Level Burn-In (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair s... [more] ICD2007-11
pp.59-64
ICD, SDM 2006-08-18
12:05
Hokkaido Hokkaido University A 65 nm Ultra-High-Density Dual-port SRAM with 0.71um2 8T-cell for SoC
Susumu Imaoka (Renesas Design), Koji Nii (Renesas Technology), Yasuhiro Masuda (Renesas Design), Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Motoshige Igarashi, Kazuo Tomita, Nobuo Tsuboi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology)
We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stabi... [more] SDM2006-148 ICD2006-102
pp.133-136
ICD, SDM 2006-08-18
14:35
Hokkaido Hokkaido University A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits
Makoto Yabuuchi, Shigeki Ohbayashi, Koji Nii, Yasumasa Tsukamoto (Renesas Technology), Susumu Imaoka (Renesas Design), Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Hiroshi Makino, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology)
 [more] SDM2006-151 ICD2006-105
pp.149-153
ICD 2006-04-14
13:50
Oita Oita University Worst-Case Ananlysis to Obtain Stable Read/Write DC Margin of High Density 6T-SRAM-Array with Local Vth Variability
Yasumasa Tsukamoto, Koji Nii (Renesas Technology), Susumu Imaoka (Renesas Design), Yuji Oda (Shikino High-Tech.), Shigeki Ohbayashi, Makoto Yabuuchi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology)
 [more] ICD2006-18
pp.97-102
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