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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD 2013-04-12
15:30		 Ibaraki Advanced Industrial Science and Technology (AIST) [Invited Lecture] Reduction of SRAM Standby Leakage utlizing All Digital Current Comparator
Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yasuhisa Shimazaki (Renesas Electronics) ICD2013-21		 A high-performance and low-leakage current embedded SRAM for mobile phones is proposed. The proposed SRAM has two low-vo... [more] ICD2013-21
pp.109-114
VLD, IPSJ-SLDM 2010-05-20
13:05		 Fukuoka Kitakyushu International Conference Center A Wide-Range Clock Synchronizer with Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS Control
Masafumi Onouchi, Yusuke Kanno, Makoto Saen, Shigenobu Komatsu (Hitachi), Yoshihiko Yasu, Koichiro Ishibashi (Renesas) VLD2010-7		 A ``wide-range voltage-and-frequency clock synchronizer'' for maintaining synchronization during voltage-scaling transit... [more] VLD2010-7
pp.67-72
ICD 2010-04-22
11:15		 Kanagawa Shonan Institute of Tech. A 40-nm Low-power SRAM with Multi-stage Replica-Bitline Scheme for Reducing Timing Variation
Shigenobu Komatsu, Masanao Yamaoka (HITACHI), Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki (Renesas Technology Corp.), Kenichi Osada (HITACHI) ICD2010-4		 A multi-stage replica bitline scheme for reducing access time by suppressing enable timing variation of a sense amplifie... [more] ICD2010-4
pp.17-21
ICD 2009-12-15
17:00		 Shizuoka Shizuoka University (Hamamatsu) A 3D Processor Using Inductive-Coupling Inter-Chip Link -- 3D System Integration of a 90nm CMOS Processor and a 65nm CMOS SRAM --
Kiichi Niitsu (Keio Univ./JST), Yasuhisa Shimazaki (Keio Univ./Renesas Technology), Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga (Keio Univ.), Itaru Nonomura (Renesas Technology), Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko Irie (Hitachi), Toshihiro Hattori, Atsushi Hasegawa (Renesas Technology), Tadahiro Kuroda (Keio Univ.) ICD2009-105		 A 90nm CMOS processor is mounted face down on a package by C4 bump and a 65nm CMOS 1MB SRAM is glued on it face up. The ... [more] ICD2009-105
pp.163-168
CPM, ICD 2008-01-17
14:30		 Tokyo Kikai-Shinko-Kaikan Bldg [Special Invited Talk] In-situ measurement of supply-noise maps with millivolt accuracy and nanosecond-order time resolution
Yusuke Kanno, Yuki Kondoh (HCRL), Takahiro Irita, Kenji Hirose, Ryo Mori, Yoshihiko Yasu (Renesas Technology, Corp.), Shigenobu Komatsu, Hiroyuki Mizuno (HCRL) CPM2007-136 ICD2007-147		 An in-situ measurement scheme for generating supply-noise maps, which can be conducted while running applications in pro... [more] CPM2007-136 ICD2007-147
pp.47-52
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