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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 9 of 9  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM, ICD 2015-08-24
10:55		 Kumamoto Kumamoto City [Invited Talk] Implementation of TFET Spice Model for Ultra-Low Power Circuit Analysis
Chika Tanaka, Akira Hokazono, Kanna Adachi, Masakazu Goto, Yoshiyuki Kondo, Emiko Sugizaki, Motohiko Fujimatsu, Hiroyuki Hara, Shinji Miyano, Keiichi Kushida, Shigeru Kawanaka (Toshiba) SDM2015-59 ICD2015-28		  [more] SDM2015-59 ICD2015-28
pp.11-13
SDM, ICD 2013-08-01
09:50		 Ishikawa Kanazawa University Scaling Strategy for Low Power RF Applications with Multi Gate Oxide Dual Work function (DWF) MOSFETs Utilizing Self-Aligned Integration Scheme
Toshitaka Miyata, Shigeru Kawanaka, Akira Hokazono, Tatsuya Ohguro, Yoshiaki Toyoshima (TOSHIBA) SDM2013-67 ICD2013-49		 Dual Work Function (DWF)-MOSFET of 100 nm gate length device with self-aligned integration scheme was demonstrated utili... [more] SDM2013-67 ICD2013-49
pp.13-18
SDM, ICD 2011-08-25
10:25		 Toyama Toyama kenminkaikan Power-Performance Estimation of Datta-Das Spin Transistor
Yoshiyuki Kondo, Shigeru Kawanaka, Kanna Adachi (Toshiba) SDM2011-74 ICD2011-42		 We report the results of power-performance analysis
of Datta-Das spin transistor(SFET) in this paper.
We clarified it... [more]		 SDM2011-74 ICD2011-42
pp.17-22
SDM, ICD 2011-08-25
10:50		 Toyama Toyama kenminkaikan Plasma Doping and Laser Spike Annealing Technique for Steep SDE Formation in nano-scale MOSFET
Emiko Sugizaki, Toshitaka Miyata, Yasunori Oshima, Akira Hokazono, Kanna Adachi, Kiyotaka Miyano, Hideji Tsujii, Shigeru Kawanaka, Satoshi Inaba, Takaharu Itani, Toshihiko Iinuma, Yoshiaki Toyoshima (Toshiba) SDM2011-75 ICD2011-43		 The importance of impurity profile design for Source/Drain Extension (SDE) is widely recognized for deeply scaled MOSFET... [more] SDM2011-75 ICD2011-43
pp.23-27
ICD, SDM 2009-07-16
15:50		 Tokyo Tokyo Institute of Technology The Study of Mobility-Tinv Trade-off in Deeply Scaled High-k/Metal Gate Devices and Scaling Design Guideline for 22nm-node Generation
Masakazu Goto, Shigeru Kawanaka, Seiji Inumiya, Naoki Kusunoki, Masumi Saitoh, Kosuke Tatsumura, Atsuhiro Kinoshita, Satoshi Inaba, Yoshiaki Toyoshima (Toshiba) SDM2009-107 ICD2009-23		 The trade-off between Tinv scaling and carrier mobility () degradation in deeply scaled HK/MG nMOSFETs has been ... [more] SDM2009-107 ICD2009-23
pp.53-56
SDM 2009-06-19
15:40		 Tokyo An401・402 Inst. Indus. Sci., The Univ. of Tokyo Intrinsic Correlation between Mobility Reduction and Vt shift due to Interface Dipole Modulation in HfSiON/SiO2 stack by La or Al addition
Kosuke Tatsumura, Takamitsu Ishihara, Seiji Inumiya, Kazuaki Nakajima, Akio Kaneko, Masakazu Goto, Shigeru Kawanaka, Atsuhiro Kinoshita (Toshiba Corp.) SDM2009-39		 Intrinsic correlation between mobility reduction by remote Coulomb scattering (RCS) and threshold voltage shift (ΔVt), b... [more] SDM2009-39
pp.71-76
ICD, SDM 2008-07-18
15:05		 Tokyo Kikai-Shinko-Kaikan Bldg. Impact of Tantalum Composition in TaCx/HfSiON Gate Stack on Device Performance of Aggressively Scaled CMOS Devices with SMT and Strained CESL
Masakazu Goto, Kosuke Tatsumura, Shigeru Kawanaka, Kazuaki Nakajima, Reika Ichihara, Yasuhito Yoshimizu, Hiroyuki Onoda, Koji Nagatomo, Toshiyuki Sasaki, Takashi Fukushima, Akiko Nomachi, Seiji Inumiya, Tomonori Aoyama, Masato Koyama, Yoshiaki Toyoshima (Toshiba Corp.) SDM2008-147 ICD2008-57		 We report TaCx/HfSiON gate stack CMOS device with simplified gate 1st process from the viewpoints of fixed charge genera... [more] SDM2008-147 ICD2008-57
pp.109-114
SDM, VLD 2007-10-30
14:10		 Tokyo Kikai-Shinko-Kaikan Bldg. Study of Parasitic Resistance Behavior and Its Extraction Method on Deeply Scaled MOSFETs
Hideji Tsujii, Akira Hokazono, Makoto Fujiwara, Shigeru Kawanaka, Atsushi Azuma, Nobutoshi Aoki, Yoshiaki Toyoshima (Toshiba) VLD2007-56 SDM2007-200		  [more] VLD2007-56 SDM2007-200
pp.27-32
ICD, SDM 2007-08-24
10:20		 Hokkaido Kitami Institute of Technology [Special Invited Talk] Effect of metal-gate/high-k on characteristics of MOSFETs for 32nm CMOS and beyond
Masato Koyama, Masahiro Koike, Yuuichi Kamimuta, Masamichi Suzuki, Kosuke Tatsumura, Yoshinori Tsuchiya, Reika Ichihara, Masakazu Goto, Koji Nagatomo, Atsushi Azuma, Shigeru Kawanaka, Kazuaki Nakajima, Katsuyuki Sekine (Toshiba Corp.) SDM2007-159 ICD2007-87		 In this paper, influences of metal-gate and high-k gate dielectric application on MOSFET (32nm node and beyond) characte... [more] SDM2007-159 ICD2007-87
pp.101-106
 Results 1 - 9 of 9  /   
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