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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 7 of 7  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
09:40
Oita B-ConPlaza Data Dependent Optimization using Suspicious Timing Error Prediction for Reconfigurable Approximation Circuits
Kazushi Kawamura, Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-80 DC2014-34
The propagation delay along each path inside an LSI widely varies depending on input data, and this property can be expl... [more] VLD2014-80 DC2014-34
pp.51-56
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
15:10
Oita B-ConPlaza A Process-Variation-Tolerant and Low-Latency Multi-Scenario High-level Synthesis Algorithm for HDR Architectures
Koki Igawa, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-86 DC2014-40
In this paper, we propose a process-variation-tolerant and low-latency multi-scenario high-level synthesis algorithm for... [more] VLD2014-86 DC2014-40
pp.105-110
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-28
15:35
Oita B-ConPlaza Energy-efficient High-level Synthesis Algorithm targeting HDR-mcv Architecture with Multiple Clock Domains and Multiple Supply Voltages
Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology/Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-102 DC2014-56
An HDR-mcv architecture, which integrates multiple supply voltages and multiple clock domains into high-level synthesis ... [more] VLD2014-102 DC2014-56
pp.203-208
CAS, SIP, MSS, VLD, SIS [detail] 2014-07-11
14:00
Hokkaido Hokkaido University A floorplan-driven high-level synthesis algorithm for reducing multiplexer inputs targeting FPGAs
Koichi Fujiwara, Shin-ya Abe, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) CAS2014-41 VLD2014-50 SIP2014-62 MSS2014-41 SIS2014-41
 [more] CAS2014-41 VLD2014-50 SIP2014-62 MSS2014-41 SIS2014-41
pp.219-224
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-29
11:40
Kagoshima   Clock Energy-efficient High-level Synthesis and Experimental Evaluation for HDR-mcd Architecture
Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech./Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-97 DC2013-63
In this paper, we propose a clock energy-efficient high-level synthesis algorithm for HDR-mcd architecture.
In HDR-mcd,... [more]
VLD2013-97 DC2013-63
pp.263-268
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
14:15
Fukuoka Centennial Hall Kyushu University School of Medicine SAAV : Energy-efficient High-level Synthesis Algorithm targeting Adaptive Voltage Huddle-based Distributed Register Architecture with Dynamic Multiple Supply Voltages
Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology Univ./Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2012-82 DC2012-48
An adaptive voltage huddle-based distributed-register architecture (AVHDR architecture), which integrates dynamic multip... [more] VLD2012-82 DC2012-48
pp.135-140
IPSJ-SLDM, VLD 2012-05-30
14:55
Fukuoka Kitakyushu International Conference Center Multiple supply voltages aware high-speed and high-efficient high-level synthesis for HDR architectures
Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2012-2
HDR architecture has been proposed as a platform that integrates energy-efficiency and interconnection delays into high-... [more] VLD2012-2
pp.7-12
 Results 1 - 7 of 7  /   
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