|
|
All Technical Committee Conferences (Searched in: All Years)
|
|
Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
|
Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
NS, IN (Joint) |
2022-03-10 09:50 |
Online |
Online |
A Study of Scalable End-to-End Overlay Network Yukihiro Togari, Shingo Okada, Hisashi Kojima (NTT) NS2021-124 |
[more] |
NS2021-124 pp.13-18 |
EMCJ, IEE-EMC |
2014-12-19 09:35 |
Shizuoka |
Shizuoka Univ. |
Fast Transient Simulation of Non-uniform Distributed Parameter Circuit with Nonlinear Device by Locally Implicit LIM Shingo Okada, Hideki Asai (Shizuoka Univ.) EMCJ2014-74 |
Locally Implicit Latency Insertion Method (LILIM) has been proposed as one of the fast transient
simulation methods of ... [more] |
EMCJ2014-74 pp.1-6 |
CAS, NLP |
2013-09-26 13:05 |
Gifu |
Satellite Campus, Gifu University |
Multi-Rate Locally Implicit Latency Insertion Method for Fast Transient Analysis of Power Distribution Network Takaaki Hojo, Shingo Okada, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) CAS2013-37 NLP2013-49 |
This report describes a multi-rate locally implicit latency insertion method (LILIM) for the fast analysis of power dist... [more] |
CAS2013-37 NLP2013-49 pp.7-12 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 13:00 |
Fukuoka |
Centennial Hall Kyushu University School of Medicine |
The Fast Transient Analysis of The Power Distribution Network Modeled by Unstructured Meshes by Using Locally Implicit Latency Insertion Method (LIM) Shingo Okada, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) VLD2012-96 DC2012-62 |
This paper describes a locally implicit latency insertion method (LILIM), which is suitable for the fast simulation of a... [more] |
VLD2012-96 DC2012-62 pp.213-218 |
IN, NV (Joint) |
2011-07-21 10:40 |
Hokkaido |
Hokkaido University |
Proposal of quick fallback system in IPv4/IPv6 Dual-stack environment Shingo Okada, Tomohiro Fujisaki (NTT) IN2011-45 |
In an IPv4/IPv6 Dual-stack environment, an IPv4/IPv6 Dual-stack node gives priority to protocol of either and communicat... [more] |
IN2011-45 pp.1-4 |
EMCJ, ITE-BCT |
2011-03-11 14:55 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Equivalent Circuit Modeling and Optimization for Reduction of Common-Mode Current in Automotive EMC Shingo Okada (Shizuoka Univ.), Takanori Uno (DENSO CORP.), Hideki Asai (Shizuoka Univ.) EMCJ2010-125 |
In this paper, first, we introduce a practical equivalent circuit modeling for the automotive electromagnetic compatibil... [more] |
EMCJ2010-125 pp.39-44 |
NS, IN (Joint) |
2008-03-07 13:10 |
Okinawa |
Bankoku Shinryokan |
Suggestion of address assignment for supporting the transition to IPv6 Shingo Okada, Naoshi Sakamoto (TDU) NS2007-203 |
During the transition to IPv6, servers must take the dual stack environment so that they can accept accesses from both I... [more] |
NS2007-203 pp.397-400 |
|
|
|
Copyright and reproduction :
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
|
[Return to Top Page]
[Return to IEICE Web Page]
|