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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS, ICD | 2022-10-25 11:25 |
Shiga | (Primary: On-site, Secondary: Online) |
Fundamental Study on Randomness Evaluation of ERO-TRNG Using APD Keiichi Ozaki, Daisuke Fujimoto (NAIST), Saki Osuka, Shinichi Kawamura (AIST), Yuichi Hayashi (NAIST)  HWS2022-33 ICD2022-25 |
Randomness evaluation of true random number generators (TRNGs) based on ring oscillators (ROs) requires an analysis of o... [more] | HWS2022-33 ICD2022-25 pp.17-22 |
| HWS, ICD | 2022-10-25 11:50 |
Shiga | (Primary: On-site, Secondary: Online) |
Optical Microscopic Observation of Semiconductor Devices toward Hardware Trojan Detection Hirofumi Sakane, Junichi Sakamoto, Shinichi Kawamura (AIST), Makoto Nagata (Kobe Univ.), Yuichi Hayashi (NAIST) HWS2022-34 ICD2022-26 |
In this paper we focus on detection of hardware Trojan (HT) in semiconductor devices under a scenario with following ste... [more] | HWS2022-34 ICD2022-26 pp.23-28 |
| EMM, BioX, ISEC, SITE, ICSS, HWS, IPSJ-CSEC, IPSJ-SPT [detail] | 2022-07-19 13:25 |
Online | Online | Revisit of Non Profiled Side Channel Analysis via Deep Learning Kentaro Imafuku, Shinichi Kawamura, Hanae Nozaki, Junichi Sakamoto, Saki Osuka (AIST) ISEC2022-8 SITE2022-12 BioX2022-33 HWS2022-8 ICSS2022-16 EMM2022-16 |
After a brief review of non-profile side channel analysis using deep learning, we propose some improved versions of the ... [more] | ISEC2022-8 SITE2022-12 BioX2022-33 HWS2022-8 ICSS2022-16 EMM2022-16 pp.7-12 |
| EMM, BioX, ISEC, SITE, ICSS, HWS, IPSJ-CSEC, IPSJ-SPT [detail] | 2022-07-19 13:50 |
Online | Online | Randomness evaluation of TERO-based TRNG with a side-channel attack countermeasure Saki Osuka (AIST), Daisuke Fujimoto, Yuichi Hayashi (NAIST), Shinichi Kawamura (AIST) ISEC2022-9 SITE2022-13 BioX2022-34 HWS2022-9 ICSS2022-17 EMM2022-17 |
True random number generators (TRNGs) based on ring oscillators (ROs) are employed in many devices because they can be c... [more] | ISEC2022-9 SITE2022-13 BioX2022-34 HWS2022-9 ICSS2022-17 EMM2022-17 pp.13-17 |
| BioX, ISEC, SITE, ICSS, EMM, HWS, IPSJ-CSEC, IPSJ-SPT [detail] | 2021-07-19 13:30 |
Online | Online | Fundamental Study on Acceleration of Inversion using Binary Extended Euclidean Algorithm for Pairing Computation in RNS Representation Kota Morimoto, Daisuke Fujimoto, Saki Osuka (NAIST), Shinichi Kawamura, Tadanori Teruya (AIST), Yuichi hayashi (NAIST) ISEC2021-10 SITE2021-4 BioX2021-11 HWS2021-10 ICSS2021-15 EMM2021-15 |
Pairing computation is an essential tool in advanced cryptography, and Yao et al. have shown that a hardware implementat... [more] | ISEC2021-10 SITE2021-4 BioX2021-11 HWS2021-10 ICSS2021-15 EMM2021-15 pp.1-7 |
| HWS | 2021-04-12 14:15 |
Tokyo | Tokyo University/Online (Primary: On-site, Secondary: Online) |
A division algorithm with constant divisor in the residue number system Shinichi Kawamura (AIST/Toshiba), Yuichi Komano (Toshiba) HWS2021-7 |
A lot of works has been done on the research of RNS (Residue Number System), which is one of the integer representations... [more] | HWS2021-7 pp.27-32 |
| ICD, HWS [detail] | 2020-10-26 14:30 |
Online | Online | Domestic Hardware Trojan Research Trends Shinichi Kawamura, Yu-ich Hayashi (AIST) HWS2020-34 ICD2020-23 |
[more] | HWS2020-34 ICD2020-23 pp.54-58 |
| ICD, HWS [detail] | 2020-10-26 14:55 |
Online | Online | Physical-Level Detection Approach against Hardware Trojans inside Semiconductor Chips (II) Hirofumi Sakane, Shinichi Kawamura, Kentaro Imafuku, Yohei Hori, Makoto Nagata, Yuichi Hayashi, Tsutomu Matsumoto (AIST) HWS2020-35 ICD2020-24 |
Hardware Trojans, known to be designed and crafted with malicious intent and deployed to be part of the hardware of the ... [more] | HWS2020-35 ICD2020-24 pp.59-64 |
| HWS | 2020-04-07 10:00 |
Online | Online | A mode for performance evaluation of Montgomery multiplication in RNS Shinichi Kawamura (ECSEC TRA) HWS2020-1 |
[more] | HWS2020-1 pp.1-6 |
| HWS, ICD [detail] | 2019-11-01 16:50 |
Osaka | DNP Namba SS Bld. | Physical-level detection approach against hardware Trojans inside semiconductor chips (I) Shinichi Kawamura, Kentaro Imafuku, Hirofumi Sakane, Yohei Hori (AIST), Makoto Nagata (AIST/Kobe Univ.), Yuichi Hayashi (AIST/NAIST), Tsutomu Matsumoto (AIST/YNU) HWS2019-65 ICD2019-26 |
It is of great concern that malicious hardware should be inserted inside semiconductor chips and on printed circuit boar... [more] | HWS2019-65 ICD2019-26 pp.47-52 |
| HWS | 2019-04-12 13:30 |
Miyagi | Tohoku University | An Improved RNS Binary Extended Euclidean Algorithm and a Residue Decoding Algorithm Shinichi Kawamura (ECSEC TRA/Toshiba/AIST), Yuichi Komano, Hideo Shimizu (Toshiba) HWS2019-1 |
[more] | HWS2019-1 pp.1-6 |
| HWS (2nd) |
2018-12-13 16:10 |
Tokyo | Tokyo Univ. Takeda Bldg. Takeda Hall | [Poster Presentation]
Computer experiments for efficient sign detection in RNS Yuya Kakei (ECSEC), Shinichi Kawamura (ECSEC/Toshiba) |
(Advance abstract in Japanese is available) [more] | |
| MWP | 2016-11-14 13:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Technology overview of high speed and stable quantum key distribution Yoshimichi Tanizawa, Akira Murakami, Alexander R. Dixon (Toshiba), James F. Dynes, Marco Lucamarini, Bernd Fröhlich, Andrew W. Sharpe, Alan Plews, Winci Tam, Zhiliang L. Yuan (Toshiba Research Europe Limited), Hideaki Sato, Shinichi Kawamura (Toshiba), Mikio Fujiwara, Masahide Sasaki (NICT), Andrew J. Shields (Toshiba Research Europe Limited) MWP2016-47 |
[more] | MWP2016-47 pp.23-27 |
| ISEC, IT, WBS | 2015-03-03 13:15 |
Fukuoka | The University of Kitakyushu | [Invited Talk]
Fast and Secure Implementation of Cryptography and its Practical Application Shinichi Kawamura (Toshiba) IT2014-99 ISEC2014-112 WBS2014-91 |
The author will talk about his past research on implementation of cryptography. For the practical use of cryptography, i... [more] | IT2014-99 ISEC2014-112 WBS2014-91 pp.231-238 |
| ISEC | 2007-09-07 15:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An Approach to Duality in Public Key Cryptosystems Kazuo Ohta (UEC), Yuichi Komano (Toshiba), Yutaka Kawai (UEC), Shinichi Kawamura (Toshiba) ISEC2007-87 |
The security of cryptosystems is formalized by the combination of adversarial goal GOAL and attack model ATK. Paillier a... [more] | ISEC2007-87 pp.99-106 |
| WBS, IT, ISEC | 2006-03-16 10:20 |
Aichi | Nagoya Univ. | Experimental Results on INSTAC-8 Compliant Board Yukiyasu Tsunoo, Toru Hisakado (NEC), Etsuko Tsujihara (Y.D.K.), Tsutomu Matsumoto (Yokohama National Univ.), Shinichi Kawamura, Kouichi Fujisaki (Toshiba) |
This paper presents the results of three kinds of Side-channel attacks, experimentally made against software-implemented... [more] | IT2005-78 ISEC2005-135 WBS2005-92 pp.81-85 |
| ISEC | 2005-05-18 13:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Ring Signature Schemes with Innocence Assertion Revisited (Part 2)
-- Group Signatures Strengthening the Signers' Privacy -- Yuichi Komano (Toshiba), Kazuo Ohta (UEC), Atsushi Shimbo, Shinichi Kawamura (Toshiba) |
This paper reconsiders the ring signature scheme with innocence assertion [10] as a group signature scheme. The ring sig... [more] | ISEC2005-2 pp.9-16 |
| ISEC, IPSJ-CSEC | 2004-07-21 09:40 |
Tokushima | Tokushima Univ. | Development of DPA evaluation platform for 8 bit processor Koichi Fujisaki, Yuki Tomoeda, Hideyuki Miyake, Yuichi Komano, Atsushi Shimbo, Shinichi Kawamura (Toshiba) |
[more] | ISEC2004-55 pp.95-102 |
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