Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
MRIS, ITE-MMS |
2018-07-06 16:35 |
Tokyo |
Waseda Univ. (Tokyo) |
Ultra-high-efficient Writing in Voltage-Control Spintronics Memory(VoCSM) Altansargai Buyandalai, Mariko Shimizu, Hiroaki Yoda, Tomoaki Inokuchi, Yuichi Ohsawa, Naoharu Shimomura, Satoshi Shirotori, Hideyurki Sugiyama, Yushi Kato, Mizue Ishikawa, Katsuhiko Koi, Soichi Oikawa, Kazutaka Ikegami, Satoshi Takaya, Shinobu Fujita, Atsushi Kurobe (Toshiba Corporation) |
[more] |
|
ICD |
2017-04-20 10:35 |
Tokyo |
(Tokyo) |
[Invited Lecture]
Sub-3 ns pulse with sub-100 uA switching of 1x-2x nm perpendicular MTJ for high-performance embedded STT-MRAM towards sub-20 nm CMOS Daisuke Saida, Saori Kashiwaad, Megumi Yakabe, Tadaomi Daibou, Junichi Ito, Hiroki Noguchi, Keiko Abe, Shinobu Fujita (Toshiba), Miyoshi Fukumoto, Shinji Miwa, Yoshishige Suzuki (Osaka Univ.) ICD2017-2 |
[more] |
ICD2017-2 pp.5-9 |
SDM |
2017-01-30 14:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
[Invited Talk]
Novel Voltage Controlled MRAM (VCM) with Fast Read/Write Circuits for Ultra Large Level Cache Yoichi Shiota (AIST), Hiroki Noguchi, Kazutaka Ikegami, Keiko Abe, Shinobu Fujita (Toshiba), Takayuki Nozaki, Shinji Yuasa (AIST), Yoshishige Suzuki (Osaka Univ.) SDM2016-135 |
In future processing system, the memory capacity of last level cache (LLC) must be increased, because LLC needs to cover... [more] |
SDM2016-135 pp.21-24 |
ICD |
2016-04-14 15:50 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
[Invited Lecture]
Power reduction based on MRAM Hiroaki Yoda, Shinobu Fujita (toshiba) ICD2016-11 |
[more] |
ICD2016-11 pp.57-59 |
ICD |
2016-04-14 16:15 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
[Invited Talk]
Technology trends and near-future applications of embedded STT-MRAM Shinobu Fujita (Toshiba) ICD2016-12 |
[more] |
ICD2016-12 pp.61-64 |
SDM |
2016-01-28 15:20 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
[Invited Talk]
MTJ based "Normally-off processors" with thermal stability factor engineered perpendicular MTJ, L2 cache based on 2T-2MTJ cell, L3 and Last Level Cache based on 1T-1MTJ cell and novel error handling scheme Kazutaka Ikegami, Hiroki Noguchi, Satoshi Takaya, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Eiji Kitagawa, Takao Ochiai, Naoharu Shimomura, Daisuke Saida, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) SDM2015-126 |
MTJ-based cache memory is expected to reduce processor power significantly. However, write energy increases rapidly for ... [more] |
SDM2015-126 pp.27-30 |
ICD |
2015-04-17 12:40 |
Nagano |
(Nagano) |
[Invited Talk]
Low-power Embedded Perpendicular STT-MRAM Design for Cache Memory Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Chika Tanaka, Chikayoshi Kamata, Minoru Amano, Eiji Kitagawa, Naoharu Shimomura, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) ICD2015-10 |
[more] |
ICD2015-10 pp.45-50 |
SDM |
2015-01-27 14:50 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
[Invited Talk]
Low power and high memory density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques Kazutaka Ikegami, Hiroki Noguchi, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Takao Ochiai, Naoharu Shimomura, Shogo Itai, Daisuke Saida, Chika Tanaka, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) SDM2014-142 |
Due to difficulty to increase clock frequency, recent processors increase cache memory to improve performance. However, ... [more] |
SDM2014-142 pp.29-32 |
ICD, CPSY |
2014-12-02 10:20 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
[Invited Talk]
Normally-Off Computing with Perpendicular STT-MRAM Hiroki Noguchi, Kazutaka Ikegami, Naoharu Shimomura, Tetsufumi Tanamoto, Junichi Ito, Shinobu Fujita (Toshiba) ICD2014-102 CPSY2014-114 |
[more] |
ICD2014-102 CPSY2014-114 pp.107-112 |
MRIS, ITE-MMS |
2014-10-03 09:30 |
Niigata |
Kashiwazaki energy hall, Niigata (Niigata) |
* Daisuke Saida, Naoharu Shimomura, Eiji Kitagawa, Chikayoshi Kamata, Megumi Yakabe, Yuuichi Osawa, Shinobu Fujita, Junichi Ito (Toshiba) MR2014-18 |
(To be available after the conference date) [more] |
MR2014-18 pp.27-31 |
ICD, SDM |
2014-08-05 11:15 |
Hokkaido |
Hokkaido Univ., Multimedia Education Bldg. (Hokkaido) |
[Invited Talk]
Low-Power and High-Speed Nonvolatile FPGA by Adjacent Integration of MONOS/Logic and Novel Programming Scheme Koichiro Zaitsu, Kosuke Tatsumura, Mari Matsumoto, Masato Oda, Shinobu Fujita, Shinichi Yasuda (Toshiba) SDM2014-75 ICD2014-44 |
Novel nonvolatile programmable switch for low-power and high-speed FPGA where MONOS flash is adjacently integrated to CM... [more] |
SDM2014-75 ICD2014-44 pp.71-76 |
ICD |
2014-04-17 14:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
[Tutorial Lecture]
Prospects of High-speed, Low-power Nonvolatile Memory STT-MRAM Shinobu Fujita (Toshiba RDC) |
[more] |
|
ICD |
2014-04-17 15:50 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
[Panel Discussion]
Perspective of emerging memories in systems and systems on emerging memories Toru Miwa (SanDisk), Koji Nii (Renesas), Shinobu Fujita (Toshiba), Hiroki Koike (Tohoku Univ.), Ken Takeuchi (Chuo Univ.) ICD2014-9 |
(To be available after the conference date) [more] |
ICD2014-9 p.45 |
SDM |
2014-01-29 13:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
[Invited Talk]
Variable Nonvolatile Memory Arrays for Adaptive Computing Systems Hiroki Noguchi, Susumu Takeda, Kumiko Nomura, Keiko Abe, Kazutaka Ikegami, Eiji Kitagawa, Naoharu Shimomura, Junichi Ito, Shinobu Fujita (Toshiba) SDM2013-141 |
[more] |
SDM2013-141 p.29 |
MRIS, ITE-MMS |
2013-07-12 16:35 |
Tokyo |
Chuo Univ. (Tokyo) |
Progress on STT MTJ writing Technology and the Effect on Normally-off Computing Systems Junichi Ito, Hiroaki Yoda, Shinobu Fujita, Naoharu Shimomura, Eiji Kitagawa, Keiko Abe, Kumiko Nomura, Hiroki Noguchi (Toshiba) MR2013-13 |
We propose a new processor using STT-MRAMs as cache memories. It enables “Normally-off computing”, where the processor i... [more] |
MR2013-13 pp.37-41 |
ICD |
2013-04-11 15:30 |
Ibaraki |
Advanced Industrial Science and Technology (AIST) (Ibaraki) |
[Invited Talk]
Novel Vertical Magnetization STT-MRAM Technologies for Reducing Power of High Performance Mobile Processors Shinobu Fujita, Keiko Abe, Hiroki Noguchi, Kumiko Nomura, Eiji Kitagawa, Naoharu Shimomura, Junichi Ito, Hiroaki Yoda (Toshiba) ICD2013-8 |
[more] |
ICD2013-8 pp.39-40 |
ICD, IPSJ-ARC |
2012-01-19 14:20 |
Tokyo |
(Tokyo) |
[Invited Talk]
Issues and Prospects of Nonvolatile Memories for Realizing Normally-Off Processors
-- How to solve the issues "Dilemma of Nonvolatile Logics -- Shinobu Fujita, Keiko Abe, Kumiko Nomura, Hiroaki Yoda (Toshiba) ICD2011-137 |
[more] |
ICD2011-137 pp.27-31 |
ICD, IPSJ-ARC |
2011-01-21 10:30 |
Kanagawa |
Keio University (Hiyoshi Campus) (Kanagawa) |
Performance Analysis of 3D-IC for Multi-Core Processors in sub-65m CMOS technologies Kumiko Nomura, Keiko Abe, Shinobu Fujita, Yasuhiko Kurosawa, Atsushi Kageshima (Toshiba) |
[more] |
ICD2010-134 pp.45-50 |
ICD, SDM |
2009-07-16 13:15 |
Tokyo |
Tokyo Institute of Technology (Tokyo) |
[Invited Talk]
Issues and Future Prospects for Large Scale Integration using CNT devices Shinobu Fujita (Toshiba Corp.) SDM2009-102 ICD2009-18 |
[more] |
SDM2009-102 ICD2009-18 pp.29-32 |
ICD, SDM |
2008-07-17 15:55 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
Co-design of CNT based devices and circuitry
-- How can CNT-based circuit overcome Si-CMOS? -- Shinobu Fujita (Toshiba RDC) SDM2008-138 ICD2008-48 |
Emerging devices using new materials (post-Si) are expected to replace Si-based MOSFET in future. This paper firstly cla... [more] |
SDM2008-138 ICD2008-48 pp.59-64 |
|