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Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS 2020-04-07 Online Online EM Analysis Attack on FPGA implementation of Binarized Neural Network
Ville Yli-Mayry, Akira Ito, Rei Ueno (Tohoku Univ.), Shivam Bhasin (Nanyang Technological Univ.), Dirmanto Jap (Nanyang Technological University), Naofumi Homma (Tohoku Univ.) HWS2020-5		  [more] HWS2020-5
pp.25-28
ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] 2019-07-24
14:10		 Kochi Kochi University of Technology Design of Highly Efficient AES Hardware Architectures Based on Multiplicative-Offset
Rei Ueno (Tohoku Univ.), Sumio Morioka (IST), Noriyuki Miura, Kohei Matsuda, Makoto Nagata (Kobe Univ.), Shivam Bhasin (NTU), Yves Mathieu, Tarik Graba, Jean-Luc Danger (TPT), Naofumi Homma (Tohoku Univ.) ISEC2019-58 SITE2019-52 BioX2019-50 HWS2019-53 ICSS2019-56 EMM2019-61		 This paper presents high throughput/gate hardware architectures. In order to achieve a high area-time efficiency, the pr... [more] ISEC2019-58 SITE2019-52 BioX2019-50 HWS2019-53 ICSS2019-56 EMM2019-61
pp.375-382
EMCJ, IEE-EMC 2014-06-20
10:35		 Hyogo Kobe Univ. Side-Channel Leakage on Silicon Substrate of CMOS Cryptographic Chip
Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata (Kobe Univ.), Yu-ichi Hayashi, Naofumi Homma (Tohoku Univ.), Shivam Bhasin, Jean-Luc Danger (Telecom Paristech) EMCJ2014-10		 Power supply currents of CMOS digital circuits partly flow through a silicon substrate in their returning (ground) paths... [more] EMCJ2014-10
pp.1-6
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