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 Results 1 - 9 of 9  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF 2017-09-25
15:25		 Tokyo DWANGO Co., Ltd. Proplsal of reconfigurable system LSI with BiCS technology -- Application to combination logic, FF, CMOS circuit and FPGA --
Shigeyoshi Watanabe (Shonan Inst. of Tech.), Tomohiro Yokota (DNP Data Techno), Shouto Tamai (Oi Electric), Takumi Sato (Japan Business Systems) RECONF2017-28		  [more] RECONF2017-28
pp.37-42
IPSJ-SLDM, SIP, IE, ICD [detail] 2010-10-05
13:20		 Chiba Makuhari Messe, International Conference Hall Study of stacked NOR type MRAM using spin transistor
Shouto Tamai, Shigeyoshi Watanabe (sit) SIP2010-55 ICD2010-69 IE2010-73		 In this paper stacked NOR type MRAM with vertical spin transistor has been newly proposed. Word line scheme surrounded b... [more] SIP2010-55 ICD2010-69 IE2010-73
pp.37-42
ICD, SDM 2010-08-27
11:40		 Hokkaido Sapporo Center for Gender Equality Study of stacked MRAM for universal memory
Shouto Tamai, Shigeyoshi Watanabe (Shonan Inst. of Tech.) SDM2010-142 ICD2010-57		 In this paper stacked NOR type MRAM with vertical spin transistor has been newly proposed. Word line scheme surrounded b... [more] SDM2010-142 ICD2010-57
pp.99-104
SDM 2010-06-22
15:55		 Tokyo An401・402 Inst. Indus. Sci., The Univ. of Tokyo Study of stacked NOR type MRAM for universal memory
Shouto Tamai, Shigeyoshi Watanabe (Shonan Inst. of Tech.) SDM2010-46		  [more] SDM2010-46
pp.73-78
ICD 2010-04-23
10:45		 Kanagawa Shonan Institute of Tech. Study of stacked NOR type MRAM
Shouto Tamai, Shigeyoshi Watanabe (sit) ICD2010-14		  [more] ICD2010-14
pp.75-80
ICD 2009-12-14
13:30		 Shizuoka Shizuoka University (Hamamatsu) [Poster Presentation] Design Technology of stacked NAND type MRAM
Shouto Tamai, Shigeyoshi Watanabe (Shonan Inst. of Tech.) ICD2009-79		 Design technology of stacked type MRAM using spin transistor has been described. Using 64 layer level cell structure fea... [more] ICD2009-79
pp.19-23
ICD, SDM 2009-07-17
09:55		 Tokyo Tokyo Institute of Technology Study of stacked NAND type MRAM for universal memory
Shouto Tamai, Shigeyoshi Watanabe (Shonan Inst. of Tech.) SDM2009-109 ICD2009-25		  [more] SDM2009-109 ICD2009-25
pp.63-68
ICD 2009-04-14
15:50		 Miyagi Daikanso (Matsushima, Miyagi) Study for Design Technology of stacked NAND type MRAM using spin transistor
Shouto Tamai, Shigeyoshi Watanabe (Shonan Inst. of Tech.) ICD2009-12		  [more] ICD2009-12
pp.59-64
ICD, SDM 2008-07-18
14:15		 Tokyo Kikai-Shinko-Kaikan Bldg. Realistic future trend of non-voltile semiconductor memory and feasibility study of ultra-low-cost high-speed universal non-volatile memory -- feasibility study of BiCS type FeRAM and MRAM --
Shigeyoshi Watanabe, Koichi Sugano, Shouto Tamai (Shonan Institute of Tech.) SDM2008-145 ICD2008-55		  [more] SDM2008-145 ICD2008-55
pp.97-102
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