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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SAT, KOSST | 2024-12-06 10:55 |
Hokkaido | nest HOTEL sapporoekimae (Primary: On-site, Secondary: Online) |
[Special Talk]
Dense Formation Flying of Multiple PicoSats for Communication Satellites and Its Technical Challenges Sumio Morioka, Takahiro Inagawa (Interstellar Technologies), Naoki Homma, Kentaro Murata (Iwate Univ.), Hirozumi Yamaguchi (Osaka Univ.), Atsushi Shirane (Institute of Science Tokyo), Minoru Okada, Keiichi Yasumoto (NAIST), Minsok Kim (Niigata Univ.)  SAT2024-55 |
[more] | SAT2024-55 pp.49-54 |
| ISEC | 2020-05-20 13:50 |
Online | Online | [Invited Talk]
Tweakable TWINE: Building a Tweakable Block Cipher on Generalized Feistel Structure (from IWSEC 2019) Kosei Sakamoto (University of Hyogo), Kazuhiko Minematsu (NEC), Nao Shibata, Maki Shigeri, Hiroyasu Kubo (NES), Yuki Funabiki (Kobe Univ.), Andrey Bogdanov (DTU), Sumio Morioka (Interstellar), Takanori Isobe (University of Hyogo/NICT) ISEC2020-7 |
[more] | ISEC2020-7 p.29 |
| ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] | 2019-07-24 14:10 |
Kochi | Kochi University of Technology | Design of Highly Efficient AES Hardware Architectures Based on Multiplicative-Offset Rei Ueno (Tohoku Univ.), Sumio Morioka (IST), Noriyuki Miura, Kohei Matsuda, Makoto Nagata (Kobe Univ.), Shivam Bhasin (NTU), Yves Mathieu, Tarik Graba, Jean-Luc Danger (TPT), Naofumi Homma (Tohoku Univ.) ISEC2019-58 SITE2019-52 BioX2019-50 HWS2019-53 ICSS2019-56 EMM2019-61 |
This paper presents high throughput/gate hardware architectures. In order to achieve a high area-time efficiency, the pr... [more] | ISEC2019-58 SITE2019-52 BioX2019-50 HWS2019-53 ICSS2019-56 EMM2019-61 pp.375-382 |
| CAS | 2012-01-19 11:15 |
Fukuoka | Kyushu Univ. | [Invited Talk]
Design Methodology of Group Signature Circuits for Cloud Servers and Clients Sumio Morioka, Jun Furukawa, Yuichi Nakamura, Kazue Sako (NEC) CAS2011-90 |
Group signature is one of the main theme in recent digital signature studies. The scheme allows users to sign anonymousl... [more] | CAS2011-90 pp.31-36 |
| VLD | 2011-03-03 11:25 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | A Low Power Hardware Architecture for Parallel Group Signature Computation Sumio Morioka, Jun Furukawa, Kazue Sako (NEC) VLD2010-128 |
We've investigated architecture of H/W accelerators for parallel group signature computation, which will be used in data... [more] | VLD2010-128 pp.69-74 |
| VLD | 2010-03-12 15:00 |
Okinawa | An ASIC implementation of a group signature algorithm using two-level behavioral synthesis Sumio Morioka, Toshinori Araki, Toshiyuki Isshiki, Satoshi Obana, Kazue Sako (NEC) VLD2009-128 |
We implemented a group signature algorithm, which enables anonymous digital signature, into an ASIC. To the best of the... [more] | VLD2009-128 pp.175-180 |
|
| ISEC, SITE, IPSJ-CSEC | 2008-07-25 09:55 |
Fukuoka | Fukuoka Institute of System LSI Design Industry | Architecture Optimization of a Group Signature Circuit Sumio Morioka, Toshinori Araki, Toshiyuki Isshiki, Satoshi Obana, Kazue Sako, Isamu Teranishi (NEC) |
Group signature scheme is one of the most active research area in recent cryptographic algorithms/applications. Typical... [more] | ISEC2008-40 pp.37-44 |
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