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 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2012-11-28
09:50		 Fukuoka Centennial Hall Kyushu University School of Medicine Performance evaluation of Via Programmable Logic VPEX using P&R tool
Taku Otani, Ryohei Hori, Taisuke Ueoka (Ritsumeikan Univ), Masaya Yoshikawa (Meijo Univ), Takeshi Fujino (Ritsumeikan Univ) VLD2012-90 DC2012-56		 We have been studying via programmable structured ASIC architecture “VPEX” which can realize arbitrary logic by customiz... [more] VLD2012-90 DC2012-56
pp.177-182
VLD 2012-03-06
10:35		 Oita B-con Plaza Performance evaluation and Improvement of Via Programmable Logic VPEX
Taku Otani, Ryohei Hori, Tatsuya Kitamori, Taisuke Ueoka (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2011-121		 We have been studying via programmable structured ASIC architecture “VPEX” which can realize arbitrary logic by customiz... [more] VLD2011-121
pp.7-12
ICD 2011-12-15
16:10		 Osaka   [Poster Presentation] Estimation of Soft Error Rate on a Via Programmable Logic "VPEX"
Taisuke Ueoka, Ryohei Hori, Tatsuya Kitamori (Ritsumeikan Univ), Masaya Yoshikawa (MeijoUniv), Takeshi Fujino (Ritsumeikan Univ) ICD2011-119		  [more] ICD2011-119
pp.93-98
VLD 2011-03-04
15:30		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center Performance Evaluation of Via Programmable ASIC Architecture VPEX3
Taisuke Ueoka, Tatsuya Kitamori, Ryohei Hori (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2010-146		 We have been studying via programmable ASIC architecture “VPEX” whose logic element (LE) consists of complex-gate type E... [more] VLD2010-146
pp.177-182
VLD 2011-03-04
15:55		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center Evaluation of Wiring Resource and Wiring Delay used in Via Programmable Logic Device VPEX
Tatsuya Kitamori, Ryohei Hori, Taisuke Ueoka (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2010-147		 We have developed a via programmable logic device using exclusive-or array (VPEX). In a VPEX, the logic is changed using... [more] VLD2010-147
pp.183-188
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2010-11-30
09:30		 Fukuoka Kyushu University Improvement and Evaluation of via programmable structured ASIC VPEX
Ryohei Hori, Tatsuya Kitamori, Taisuke Ueoka (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) CPM2010-132 ICD2010-91		  [more] CPM2010-132 ICD2010-91
pp.49-54
 Results 1 - 6 of 6  /   
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