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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 34  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
MVE, IPSJ-CVIM, VRSJ-SIG-MR 2023-01-27
10:25
Nara Nara Institute of Science and Technology
(Primary: On-site, Secondary: Online)
Estimating the subjective impression of presentation viewers using EEG
Takahiro Morita, Liang Zhang, Atsushi Nagate (SoftBank), Maryam Alimardani, Shuichi Nishio (Osaka Univ)
 [more]
MRIS, ITE-MMS 2022-12-08
13:30
Ehime Ehime Univ. + Online
(Primary: On-site, Secondary: Online)
3D magnetic memory with artificial ferromagnet
Teruo Ono, Yu Min Hung, Heechan Jang, Feifan Ye, Ryosuke Hisatomi, Shiota Youichi, Takahiro Moriyama (Kyoto Univ.) MRIS2022-18
 [more] MRIS2022-18
pp.1-6
SDM 2022-11-11
13:00
Online Online [Invited Talk] Understanding of Electron Mobility Limiting Factor in Cryo-CMOS
Hiroshi Oka, Takumi Inaba, Shota Iizuka, Hidehiro Asai, Kimihiko Kato, Takahiro Mori (AIST) SDM2022-74
To realize highly-integrated quantum computers, the Cryo-CMOS circuit has attracted significant attention for control/re... [more] SDM2022-74
p.49
ICD, SDM, ITE-IST [detail] 2022-08-09
11:05
Online   [Invited Talk] Effect of Conduction Band Edge States on Coulomb-Limiting Electron Mobility in Cryogenic MOSFET Operation
Hiroshi Oka, Takumi Inaba, Shota Iizuka, Hidehiro Asai, Kimihiko Kato, Takahiro Mori (AIST) SDM2022-46 ICD2022-14
Cryogenic-CMOS technology has attracted significant attention for control/read-out qubits for realizing a large-scale qu... [more] SDM2022-46 ICD2022-14
pp.54-59
ICD, SDM, ITE-IST [detail] 2022-08-09
11:50
Online   TCAD Analysis for threshold voltage increase in cryogenic MOSFET operation
Hidehiro Asai, Takumi Inaba, Junichi Hattori, Koichi Fukuda, Hiroshi Oka, Takahiro Mori (AIST) SDM2022-47 ICD2022-15
 [more] SDM2022-47 ICD2022-15
pp.60-63
IMQ, HIP 2022-07-08
13:25
Hokkaido Satellite Campus, Sapporo City University Estimating the subjective impression of presentation viewers using EEG
Takahiro Morita, Liang Zhang, Atsushi Nagate (SoftBank), Maryam Alimardani, Shuichi Nishio (Osaka Univ) IMQ2022-5 HIP2022-36
(To be available after the conference date) [more] IMQ2022-5 HIP2022-36
pp.5-10
RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] 2022-01-24
09:55
Online Online Study on Reverse Converters for RNS moduli set {2^k,2^n+1,2^n-1} using Signed-Digit numbers
Takahiro Morii, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2021-50 CPSY2021-19 RECONF2021-58
In this study, we propose reverse converters for moduli set ${2^k,2^n+1,2^n-1}$ that convert residue number system to we... [more] VLD2021-50 CPSY2021-19 RECONF2021-58
pp.7-12
SDM 2021-10-21
14:30
Online Online [Invited Talk] Device and Integration Technologies Realizing Silicon Quantum Computers
Takahiro Mori (AIST) SDM2021-49
 [more] SDM2021-49
p.20
SDM, ICD, ITE-IST [detail] 2021-08-17
10:15
Online Online [Invited Talk] Buried nanomagnet realizing high-speed/low-variability silicon spin qubits: implementable in error-correctable large-scale quantum computers
Shota Iizuka, Kimihiko Kato, Atsushi Yagishita, Hidehiro Asai, Tetsuya Ueda, Hiroshi Oka, Junichi Hattori, Tsutomu Ikegami, Koichi Fukuda, Takahiro Mori (AIST) SDM2021-30 ICD2021-1
We propose a buried nanomagnet (BNM) realizing high-speed/low-variability silicon spin qubit operation, inspired by buri... [more] SDM2021-30 ICD2021-1
pp.1-6
SDM 2021-06-22
15:20
Online Online [Invited Lecture] Development of TFET-based qubits enabling high-temperature operation to realize silicon-based quantum computing
Takahiro Mori (AIST) SDM2021-25
Quantum computers have been attractive because they could realize large-scale and highly complicated calculations that c... [more] SDM2021-25
p.16
ICD, SDM, ITE-IST [detail] 2020-08-07
09:30
Online Online [Invited Talk] Understanding the Origin of Low-frequency Noise in Cryo-CMOS Toward Long-coherence-time Si Spin Qubit
Hiroshi Oka, Takashi Matsukawa, Kimihiko Kato, Shota Iizuka, Wataru Mizubayashi, Kazuhiko Endo, Tetsuji Yasuda, Takahiro Mori (AIST) SDM2020-6 ICD2020-6
Si quantum computer has attracted a significant attention due to its potential for large-scale integration using semicon... [more] SDM2020-6 ICD2020-6
pp.25-30
SDM 2017-11-09
13:05
Tokyo Kikai-Shinko-Kaikan Bldg. Simple and efficient approach to improve hot carrier immunity of a p-LDMOSFET
Atsushi Sakai, Katsumi Eikyu (REL), Fujii Hiroki, Takahiro Mori (RSMC), Yutaka Akiyama, Yasuo Yamaguchi (REL) SDM2017-63
This paper proposes a simple and efficient method to improve hot carrier (HC) immunity of p-channel LDMOSFET without deg... [more] SDM2017-63
pp.11-14
SDM, ICD, ITE-IST [detail] 2017-07-31
12:00
Hokkaido Hokkaido-Univ. Multimedia Education Bldg. TCAD Simulation of C-TFET Circuit with Drain Offset Structure
Hidehiro Asai, Takahiro Mori, Junich Hattori, Koichi Fukuda, Kazuhiko Endo, Takashi Matsukawa (AIST) SDM2017-35 ICD2017-23
We have performed TCAD simulation for a ring oscillator composed of complementary Tunnel Field Effect Transistors (C-TFE... [more] SDM2017-35 ICD2017-23
pp.21-24
SDM 2017-01-30
10:00
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Demonstrating Performance Improvement of Complementary TFET Circuits by ION Enhancement Based on Isoelectronic Trap Technology
Takahiro Mori, Hidehiro Asai, Junichi Hattori, Koichi Fukuda, Shintaro Otsuka, Yukinori Morita, Shin-ichi O'uchi, Hiroshi Fuketa, Shinji Migita, Wataru Mizubayashi, Hiroyuki Ota, Takashi Matuskawa (ANational Institute of Advanced Industrial ScieIST) SDM2016-130
We improved the performance of a complementary circuit comprising Si-based tunnel field-effect transistors (TFETs) by us... [more] SDM2016-130
pp.1-4
ICD, SDM, ITE-IST [detail] 2016-08-03
09:00
Osaka Central Electric Club [Invited Talk] SRAM PUF using Polycrystalline Silicon Channel FinFET and Its Evaluation
Shin-ichi O'uchi, Yungxun Liu, Yohei Hori, Toshifumi Irisawa, Hiroshi Fuketa, Yukinori Morita, Shinji Migita, Takahiro Mori, Tadashi Nakagawa, Junichi Tsukada, Hanpei Koike, Meishoku Masahara, Takashi Matsukawa (AIST) SDM2016-60 ICD2016-28
 [more] SDM2016-60 ICD2016-28
pp.83-87
SDM 2016-01-28
11:00
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Understanding of BTI for Tunnel FETs
Wataru Mizubayashi, Takahiro Mori, Koichi Fukuda, Yuki Ishikawa, Yukinori Morita, Shinji Migita, Hiroyuki Ota, Yongxun Liu, Shinichi O'uchi, Junichi Tsukada, Hiromi Yamauchi, Takashi Matsukawa, Meishoku Masahara, Kazuhiko Endo (AIST) SDM2015-122
(To be available after the conference date) [more] SDM2015-122
pp.9-12
SDM 2015-06-19
17:10
Aichi VBL, Nagoya Univ. [Invited Lecture] Fabrication and Characterization of MoS2 MOSFET with High-k/Metal Gate
Takahiro Mori (AIST), Naruki Ninomiya (YNU), Noriyuki Uchida, Toshitaka Kubo (AIST), Eiichiro Watanabe, Daiju Tsuya, Satoshi Moriyama (NIMS), Masatoshi Tanaka (YNU), Atsushi Ando (AIST) SDM2015-56
We report the device fabrication and characterization of the high-k/metal gate MoS2 MOSFETs. To investigate the scatteri... [more] SDM2015-56
pp.99-103
SDM 2015-01-27
11:15
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] High-performance tri-gate poly-Ge Junction-less p- and n-MOSFETs Fabricated by Flash Lamp Annealing Process
Koji Usuda, Yoshiki Kamata, Yuuichi Kamimuta, Takahiro Mori, Masahiro Koike, Tsutomu Tezuka (AIST) SDM2014-138
Poly-crystalline Ge (poly-Ge) layer can be candidate for the channel of stacking 3D-CMOS from the viewpoint of low-therm... [more] SDM2014-138
pp.13-16
SDM 2015-01-27
15:30
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Accurate Prediction of PBTI Lifetime in N-type Fin-Channel High-k Tunnel FETs
Wataru Mizubayashi, Takahiro Mori, Koichi Fukuda, Yongxun Liu, Takashi Matsukawa, Yuki Ishikawa, Kazuhiko Endo, Shinichi Ohuchi, Junichi Tsukada, Hiromi Yamauchi, Yukinori Morita, Shinji Migita, Hiroyuki Ota, Meishoku Masahara (AIST) SDM2014-143
The positive bias temperature instability (PBTI) characteristics for n-type fin-channel tunnel FETs (TFETs) with high-k ... [more] SDM2014-143
pp.33-36
SDM 2015-01-27
16:45
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Experimental Realization of Complementary p- and n- Tunnel FinFETs with Subthreshold Slopes of Less than 60 mV/decade and Very Low (pA/um) Off-Current on a Si CMOS Platform
Yukinori Morita, Takahiro Mori, Koichi Fukuda, Wataru Mizubayashi, Shinji Migita, Takashi Matsukawa, Kazuhiko Endo, Shinichi O'uchi, Yongxun Liu, Meishoku Masahara, Hiroyuki Ota (AIST) SDM2014-146
Complementary (p- and n-type) tunnel FinFETs operating with subthreshold slopes (SSs) of less than 60 mV/decade and very... [more] SDM2014-146
pp.45-48
 Results 1 - 20 of 34  /  [Next]  
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