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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-26
16:40
Kanagawa Hiyoshi Campus, Keio University Study of pattern area and reconfigurable logic circuit with DG/CNT transistor
Takamichi Hayashi, Shigeyoshi Watanabe (SIT) VLD2011-119 CPSY2011-82 RECONF2011-78
Pattern area for 2~6 input reconfigurable logic circuit with double-gate (DG), Carbon-Nano-Tube (CNT), double-gate and C... [more] VLD2011-119 CPSY2011-82 RECONF2011-78
pp.163-168
SDM, ICD 2011-08-25
09:50
Toyama Toyama kenminkaikan Study of pattern area for reconfigurable logic circuit with DG/CNT transistor
Takamichi Hayashi, Shigeyoshi Watanabe (SIT) SDM2011-73 ICD2011-41
Pattern area for 2~6 input reconfigurable logic circuit with double-gate (DG), Carbon-Nano-Tube (CNT), double-gate and C... [more] SDM2011-73 ICD2011-41
pp.13-16
ICD, SDM 2010-08-27
15:10
Hokkaido Sapporo Center for Gender Equality Circuit design of reconfigurable logic based on MOS double gate/Carbon Nano Tube transistor
Takamichi Hayashi, Shigeyoshi Watanabe (Shonan Inst. of Tech.) SDM2010-148 ICD2010-63
Reconfigurable logic for more than 3input based on MOS double gate / Carbon Nano Tube transistor has been newly proposed... [more] SDM2010-148 ICD2010-63
pp.131-136
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