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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM, ICD, ITE-IST [detail] | 2021-08-17 11:00 |
Online | Online (Online) | [Invited Talk]
Development of 144-bit CMOS Annealing Processor with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems Takashi Takemoto, Kasho Yamamoto, Chihiro Yoshimura, Mashiro Mayumi, Masanao Yamaoka (Hitachi)  SDM2021-31 ICD2021-2 |
[more] | SDM2021-31 ICD2021-2 pp.7-11 |
| SDM, ICD, ITE-IST [detail] | 2019-08-07 13:30 |
Hokkaido | Hokkaido Univ., Graduate School /Faculty of Information Science and (Hokkaido) | [Invited Talk]
A Scalable CMOS Annealing Processor for Solving Large-scale Combinatorial Optimization Problems Masato Hayashi, Takashi Takemoto, Chihiro Yoshimura, Masanao Yamaoka (Hitachi) SDM2019-36 ICD2019-1 |
This paper presents a CMOS annealing processor (CMOS-AP) that accelerates ground state searches of the Ising model. The ... [more] | SDM2019-36 ICD2019-1 pp.1-5 |
| RECONF, CPSY, DC, IPSJ-ARC (Joint) [detail] |
2017-05-23 15:10 |
Hokkaido | Noboribetsu-Onsen Dai-ichi-Takimoto-Kan (Hokkaido) | CPSY2017-4 DC2017-4 RECONF2017-21 |
A CMOS Ising Computing based on Ising model, which effectively solves combinational optimization problems necessary for ... [more] | CPSY2017-4 DC2017-4 RECONF2017-21 pp.15-20(CPSY), pp.15-20(DC), pp.111-116(RECONF) |
| CPM, OPE, LQE, R, EMD | 2015-08-28 10:30 |
Aomori | Aomori-Bussankan-Asupamu (Aomori) | A 50-Gb/s Optical Transmitter Using a Lens-integrated DFB-LD and a Laser Diode Driver based on 0.18-um SiGe Process Takashi Takemoto, Yasunobu Matsuoka, Hidenori Yonezawa, Hiroki Yamashita, Koichiro Adachi, Takahiro Nakamura, Hideo Arimoto (Hitachi) R2015-39 EMD2015-47 CPM2015-63 OPE2015-78 LQE2015-47 |
The current explosive increase in the data traffic causes a rapid expansion in the total throughput for intra-rack and r... [more] | R2015-39 EMD2015-47 CPM2015-63 OPE2015-78 LQE2015-47 pp.81-86 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 14:45 |
Oita | B-ConPlaza (Oita) | [Invited Talk]
25-Gb/s CMOS Optical Transceiver for Board-to-board Interconnects Takashi Takemoto, Hiroki Yamashita, Yasunobu Matsuoka (Hitachi) CPM2014-128 ICD2014-71 |
The current explosive increase in the data traffic causes a rapid expansion in the total throughput for board-to-board s... [more] | CPM2014-128 ICD2014-71 pp.33-38 |
| OCS, OPE, LQE | 2014-10-30 16:20 |
Nagasaki | Nagasaki Museum of History and Culture (Nagasaki) | A vertically illuminated Germanium Photodiode for 25Gbps multi-mode-fiber optical interconnect Tadashi Okumura, Yuki Wakayama, Yasunobu Matsuoka, Katsuya Oda, Misuzu Sagawa, Takashi Takemoto, Etsuko Nomoto, Hideo Arimoto, Shigehisa Tanaka (Hitachi) OCS2014-65 OPE2014-109 LQE2014-83 |
For a multi mode fiber optical link, a high speed silicon photonics receiver based on a highly alignment tolerant vertic... [more] | OCS2014-65 OPE2014-109 LQE2014-83 pp.123-126 |
| OCS, LQE, OPE | 2011-10-27 15:40 |
Kochi | Kochi University of Technology (Kochi) | 25Gbit/s Optical Tranceiver Using Lens Integrated Optical Deices and CMOS Integrated Circuit for Optical Interconnects Daichi Kawamura, Toshiaki Takai, Yong Lee, Yasunobu Matsuoka, Koichiro Adachi, Norio Chujo, Kenji Kogo, Saori Hamamura, Takashi Takemoto, Hiroki Yamashita, Toshiki Sugawara, Shinji Tsuji (Hitachi) OCS2011-69 OPE2011-107 LQE2011-70 |
We developed the high-speed optical transceiver for board-to-board and rack-to-rack optical interconnects. Lens integrat... [more] | OCS2011-69 OPE2011-107 LQE2011-70 pp.81-85 |
| PN, OCS, NS (Joint) |
2011-06-23 12:55 |
Wakayama | Wakayama University (Wakayama) | A Compact 4 × 25-Gb/s 3.0 mW/Gbps CMOS-based Optical Receiver for Optical Backplane Takashi Takemoto, Fumio Yuki, Hiroki Yamashita, Shinji Tsuji, Yong Lee, Shinji Nishimura (Hitachi) OCS2011-12 |
(Advance abstract in Japanese is available) [more] | OCS2011-12 pp.7-12 |
| IA | 2010-02-19 13:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Tokyo) | Development of power-saving and high-performance optical I/O technologies for 40G/100G Ethernet standard Hiroshi Onaka, Tadashi Ikeuchi (PETRA/Fujitsu), Shinji Tsuji, Takashi Takemoto (PETRA/Hitachi), Shigeyuki Yanagimachi (PETRA/NEC), Masahito Tomizawa, Shigeki Aisawa (PETRA/NTT), Yasuhiko Arakawa (Univ. of Tokyo.) IA2009-89 |
We introduce the latest result of "Development project of power-saving and high-performance optical I/O technologies pro... [more] | IA2009-89 pp.41-46 |
| IA | 2009-01-28 14:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Tokyo) | Development of power-saving and high-performance optical I/O technologies Hiroshi Onaka, Tadashi Ikeuchi (Fujitsu Limited/OITDA), Shinji Tsuji, Takashi Takemoto (itachi/OITDA), Ryosuke Kuribayashi, Shigeyuki Yanagimachi (NEC/OITDA), Masahito Tomizawa, Shigeki Aisawa (ＮＴＴ/OITDA), Yasuhiko Arakawa (Tokyo Unv.) IA2008-53 |
We introduce the "Development project of power-saving and high-performance optical I/O technologies" to realize 40Gbps a... [more] | IA2008-53 pp.35-38 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 16:25 |
Fukuoka | Kitakyushu International Conference Center (Fukuoka) | FTN Simulation Technology Based on Analysis of Frequency, Time and Noise for High-speed Serial Communication System Goichi Ono, Takashi Takemoto, Koji Fukuda, Fumio Yuki, Ryo Nemoto, Eiichi Suzuki, Masayoshi Yagyu, Hiroki Yamashita, Tatsuya Saito (Hitachi) CPSY2007-38 |
We introduce a FTN simulation technology and its circuit behavior models for a high-speed serial communication system be... [more] | CPSY2007-38 pp.19-24 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 16:50 |
Fukuoka | Kitakyushu International Conference Center (Fukuoka) | The Evaluation of High-speed Serial Communication System by Using FTN Simulation Technology Takashi Takemoto, Goichi Ono, Koji Fukuda, Fumio Yuki, Ryo Nemoto, Eiichi Suzuki, Masayoshi Yagyu, Hiroki Yamashita, Tatsuya Saito (Hitachi) CPSY2007-39 |
We describe a FTN simulation technology for high-speed serial interface which is high-accuracy behavior model based on a... [more] | CPSY2007-39 pp.25-30 |
| IE, SIP, ICD, IPSJ-SLDM | 2004-10-22 09:20 |
Yamagata | (Yamagata) | 3D Graphics Processor for Mobile Set based on Configurable Processor Takashi Takemoto, Yasuharu Takenaka, Tsutomu Minagawa, Tomohiro Koizumi, Yasuyuki Ushijima, Naoaki Yanagida, Yasuo Ohara, Kouichi Tanaka, Yasuhiko Fujita (Toshiba Corp.) |
A media processor named T4G is described. T4G integrates 3.5M polygon/sec 3D Graphic engine, 15fps@QVGA MPEG4 engine, 2M... [more] | SIP2004-89 ICD2004-121 IE2004-65 pp.1-6 |
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