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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 12 of 12  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS
(2nd)
2019-12-06
16:00
Tokyo Asakusabashi Hulic Conference [Poster Presentation] Model Reverse-Engineering Attack using Correlation Power Analysis against Systolic Array Based Neural Network Accelerator
Kota Yoshida, Shunsuke Okura, Mitsuru Shiozaki, Takaya Kubota, Takeshi Fujino (Ritsumeikan Univ.)
 [more]
HWS 2019-04-12
15:05
Miyagi Tohoku University Implementation and Experimental Evaluation of Physically Unclonable Functions in 180nm CMOS Process
Mitsuru Shiozaki, Takaya Kubota, Masayoshi Shirahata (Ritsumeikan Univ.), Yohei Hori, Toshihiro Katashita (AIST), Takeshi Fujino (Ritsumeikan Univ.) HWS2019-4
Evaluation items and evaluation schemes of Physically Unclonable Function (PUF) are discussed in international standardi... [more] HWS2019-4
pp.19-24
HWS, VLD 2019-02-28
17:10
Okinawa Okinawa Ken Seinen Kaikan Error correction method for PUF utilizing the Pixel Variation in the CMOS Image Sensor
Ryota Ishiki, Masayoshi Shirahata (Ritsumeikan Univ.), Shunsuke Okura (Brillnics), Mitsuru Shiozaki, Takaya Kubota (Ritsumeikan Univ.), Kenichiro Ishikawa, Isao Takayanagi (Brillnics), Takeshi Fujino (Ritsumeikan Univ.) VLD2018-121 HWS2018-84
(To be available after the conference date) [more] VLD2018-121 HWS2018-84
pp.169-174
ICD, CPSY, CAS 2018-12-23
09:30
Okinawa   [Poster Presentation] Proposal of security system using CMOS Image Sensor PUF
Shiori Inoue, Ryota Issiki, Shohei Takano, Masayosi Shirahata (Ritsumeikan Univ.), Shunsuke Okura (Brillnics Inc.), Mitsuru Shiozaki, Takaya Kubota (Ritsumeikan Univ.), Kenichiro Ishikawa, Isao Takayanagi (Brillnics Inc.), Takeshi Fujino (Ritsumeikan Univ.) CAS2018-96 ICD2018-80 CPSY2018-62
(To be available after the conference date) [more] CAS2018-96 ICD2018-80 CPSY2018-62
pp.77-80
HWS
(2nd)
2018-03-03
14:20
Okinawa   Implementation Evaluation of Secure Key Generation from MDR-ROM PUF for In-Vehicle Network
Takuro Kusunoki, Yuya Muragishi, Mitsuru Shiozaki, Takaya Kubota, Takeshi Fujino (Ritsumeikan Univ.)
(Advance abstract in Japanese is available) [more]
HWS
(2nd)
2018-03-03
15:55
Okinawa   Utilization of side-channel information for improving fuzz testing on in-vehicle microcomputer
Ryosuke Taniguchi, Takaya kubota, Mitsuru Shiozaki, Masayoshi Shirahata, Takeshi Fujino (Ritsumeikan Univ.)
(Advance abstract in Japanese is available) [more]
CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] 2015-03-06
13:25
Kagoshima   Implementation evaluation of in-vehicle encrypted CAN communication and replay attack countermeasure technique
Masashi Nakano, Takaya Kubota, Mitsuru Shiozaki, Takeshi Fujino (Ritsumeikan Univ.) CPSY2014-163 DC2014-89
As advanced electronic in-vehicle network has recently become prevalent as can be seen in such as safety driving support... [more] CPSY2014-163 DC2014-89
pp.7-12
CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] 2014-03-15
18:05
Okinawa   Design and implementation of tamper-resistant authentication system for vehicle installation using PUF and side-channel attacks resistant AES.
Masashi Nakano, Shintaro Ukai, Megumi Shibatani, Takaya Kubota, Mitsuru Shiozaki, Takeshi Fujino (Ritsumeikan Univ.) CPSY2013-106 DC2013-93
Recently, IC chips implementing encryption circuit is widely used in various applications such as electronic money, cred... [more] CPSY2013-106 DC2013-93
pp.139-144
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-27
10:20
Kagoshima   Performance Evaluation of Tamper-Resistant AES Cryptographic Circuit utilizing Hybrid Masking Dual-Rail ROM
Shintaro Ukai, Tsunato Nakai, Toshiki Kitamura, Takaya Kubota, Mitsuru Shiozaki, Takeshi Fujino (Ritsumeikan Univ.) CPM2013-111 ICD2013-88
Tamper-resistant devices require to protect cryptographic circuit from side-channel attacks such as power analysis (PA) ... [more] CPM2013-111 ICD2013-88
pp.19-24
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-28
10:55
Fukuoka Centennial Hall Kyushu University School of Medicine AES Cryptographic Circuit utilizing Dual-Rail RSL Memory Technique
Yuki Hashimoto, Mitsuru Shiozaki, Takaya Kubota, Takeshi Fujino (Ritsumeikan Univ.) CPM2012-120 ICD2012-84
Tamper LSI design methodology has to be applied in order to implement secure cryptographic circuit, which is resistant t... [more] CPM2012-120 ICD2012-84
pp.43-48
RECONF 2012-09-18
13:20
Shiga Epock Ritsumei 21, Ritsumeikan Univ. [Invited Talk] The LSI Design Methodology of Tamper Resistant Cryptographic Circuit
Takeshi Fujino, Mitsuru Shiozaki, Takaya Kubota (Ritsumeikan Univ.), Masaya Yoshikawa (Meijyo Uiv.) RECONF2012-29
Tamper LSI Design Methodology have to be applied in order to implement secure cryptographic circuit which is resistant t... [more] RECONF2012-29
pp.31-36
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-UBI, IPSJ-MBL [detail] 2010-03-28
14:15
Tokyo   Development of a URL Filtering System for Ultra-high Speed Networks
Kenji Toda, Mamoru Sekiyama, Takaya Kubota (AIST) CPSY2009-92 DC2009-89
The FPGA board having two DDR2 ports and six 10GbE ports is developed and implemented hybrid method using hash and binar... [more] CPSY2009-92 DC2009-89
pp.483-488
 Results 1 - 12 of 12  /   
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