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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
DC |
2010-02-15 11:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A Method of Reproducing Iuput/Ouput Error Trace on High-level Design for Hardware Debug Support Yeonbok Lee, Tasuku Nishihara, Takeshi Matsumoto (Univ. of Tokyo.), Masahiro Fujita (Univ. of Tokyo./JST) DC2009-69 |
[more] |
DC2009-69 pp.25-30 |
DC, CPSY, IPSJ-SLDM, IPSJ-EMB |
2009-03-05 17:30 |
Niigata |
Sado Island Integrated Development Center |
Debugging Support for Synchronization of Parallel Execution in System Level Designs Hiroki Harada, Tasuku Nishihara, Takeshi Matsumoto (Tokyo University), Masahiro Fujita (Tokyo University/JST) CPSY2008-94 DC2008-85 |
There are many high-level designs contain parallel execution, synchronization, or communication, and they are often erro... [more] |
CPSY2008-94 DC2008-85 pp.37-42 |
VLD, CPSY, RECONF, IPSJ-SLDM |
2009-01-30 08:40 |
Kanagawa |
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Automatic Equivalence Specification between Two Sequential Circuits in High-level Design Jinmei Xu, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita (University of Tokyo) VLD2008-109 CPSY2008-71 RECONF2008-73 |
[more] |
VLD2008-109 CPSY2008-71 RECONF2008-73 pp.105-110 |
VLD, CPSY, RECONF, IPSJ-SLDM |
2009-01-30 09:05 |
Kanagawa |
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Formal Verification Method for Protocol Transducer Using Automatically Generated Properties from Specification Fei Gao, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo) VLD2008-110 CPSY2008-72 RECONF2008-74 |
IP-reuse design is widely applied in order to reduce design period by utilizing already designed and well verified modul... [more] |
VLD2008-110 CPSY2008-72 RECONF2008-74 pp.111-116 |
DC, CPSY, IPSJ-SLDM, IPSJ-EMB |
2008-03-28 10:30 |
Kagoshima |
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A technique of automatic input pattern generation for system-level design descriptions by concrete and symbolic simulations Yoshihisa Kojima, Tasuku Nishihara, Takeshi Matsumoto (Univ. of Tokyo), Masahiro Fujita (VDEC, Univ of Tokyo) DC2007-106 CPSY2007-102 |
As the VLSI systems grow larger and more complicated, it becomes more difficult to manually prepare the input patterns o... [more] |
DC2007-106 CPSY2007-102 pp.133-138 |
VLD, ICD |
2008-03-06 15:05 |
Okinawa |
TiRuRu |
Performance Estimation considering False-paths for System-level Design Daisuke Ando, Takeshi Matsumoto, Tasuku Nishihara, Masahiro Fujita (Univ. of Tokyo) VLD2007-152 ICD2007-175 |
In designing today's highly complicated system-LSIs, it is essential to estimate timing information such as worst-case o... [more] |
VLD2007-152 ICD2007-175 pp.49-54 |
ICD, VLD |
2007-03-07 15:20 |
Okinawa |
Mielparque Okinawa |
Design Checker for System-Level Design using Extended System Dependence Graph Daisuke Ando, Takeshi Matsumoto, Tasuku Nishihara, Masahiro Fujita (Univ. of Tokyo) |
In designing system LSI or System-on-a-Chip (SoC), it is essential to find and correct design errors as early design sta... [more] |
VLD2006-112 ICD2006-203 pp.37-42 |
ICD, VLD |
2006-03-09 09:15 |
Okinawa |
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Verifying Deep Bugs by Model Checking and Inductive Approach Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita (Tokyo Univ.) |
[more] |
VLD2005-108 ICD2005-225 pp.1-6 |
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