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Conference Papers (Available on Advance Programs) (Sort by: Date Descending)

Committee	Date Time	Place		Paper Title / Authors	Abstract	Paper #
CPM, LQE, ED	2016-12-12 15:20	Kyoto	Kyoto University	Evaluating Current Collapse of GaN HEMT devices by Carrier Number Kohei Oasa, Akira Yoshioka, Yasunobu Saito, Takuo Kikuchi, Tatsuya Ohguro, Takeshi Hamamoto, Toru Sugiyama (TOSHIBA) ED2016-62 CPM2016-95 LQE2016-78	We report a new method to evaluate current collapse. To exclude self-heating effect during dynamic test, we propose carr... [more]	ED2016-62 CPM2016-95 LQE2016-78 pp.27-30
SDM, ICD	2013-08-01 09:50	Ishikawa	Kanazawa University	Scaling Strategy for Low Power RF Applications with Multi Gate Oxide Dual Work function (DWF) MOSFETs Utilizing Self-Aligned Integration Scheme Toshitaka Miyata, Shigeru Kawanaka, Akira Hokazono, Tatsuya Ohguro, Yoshiaki Toyoshima (TOSHIBA) SDM2013-67 ICD2013-49	Dual Work Function (DWF)-MOSFET of 100 nm gate length device with self-aligned integration scheme was demonstrated utili... [more]	SDM2013-67 ICD2013-49 pp.13-18
SDM	2011-11-10 13:50	Tokyo	Kikai-Shinko-Kaikan Bldg.	[Invited Talk] Comprehensive Understanding of Random Telegraph Noise with Physics Based Simulation Yusuke Higashi, Nobuyuki Momo, Hisayo S. Momose, Tatsuya Ohguro, Kazuya Matsuzawa (Toshiba) SDM2011-118	Physical modeling of transient and frequency domain noise simulation for random telegraph noise (RTN) is conducted, cons... [more]	SDM2011-118 pp.17-20
ICD, ITE-IST	2008-10-23 11:10	Hokkaido	Hokkaido University	[Invited Talk] Analog/RF performance of scaled MOSFET -- Is scaled MOSFET friend for analog/RF circuits? -- Tatsuya Ohguro (Toshiba) ICD2008-74	High performance has been realized by gate length scaling of MOSFET. Recently, not only gate length scaling but also ag... [more]	ICD2008-74 pp.89-94
ICD, ITE-IST	2008-10-23 16:05	Hokkaido	Hokkaido University	[Panel Discussion] Challenges and Future of Analog Circuit Design using Sub-100nm CMOS Devices Shoji Kawahito (Shizuoka Univ.), Shigetoshi Sugawa (Tohoku Univ.), Tatsuya Ohguro (Toshiba), Hidetoshi Onodera (Kyoto Univ.), Kunihiko Goto (Fujitsu Labs.), Toshihiko Hamasaki (TI), Shiro Dosho (Panasonic)	[more]
ICD, SDM	2008-07-17 11:20	Tokyo	Kikai-Shinko-Kaikan Bldg.	[Invited Talk] Progress of compact model for CMOS circuit design -- Performance of HiSIM model based on the surface potential model -- Tatsuya Ohguro (Hiroshima Univ./Toshiba), Mitiko Miura-Mattausch (Hiroshima Univ.) SDM2008-133 ICD2008-43	HiSIM model based on the surface potential model has been popular because the model can accurately simulate analog and R... [more]	SDM2008-133 ICD2008-43 pp.29-34
ICD, SDM	2005-08-19 10:45	Hokkaido	HAKODATE KOKUSAI HOTEL	HfSiON Gate Dielectrics Design for Mixed Signal CMOS Kenji Kojima, Ryosuke Iijima, Tatsuya Ohguro, Takeshi Watanabe, Mariko Takayanagi, Hisayo S. Momose, Kazunari Ishimaru, Hidemi Ishiuchi (TOSHIBA)	(Advance abstract in Japanese is available) [more]	SDM2005-147 ICD2005-86 pp.25-30

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