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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, ITE-CE 2007-12-14
14:40		 Kochi   A multi matrix-processor core architecture for real-time image processing SoC
Katsuya Mizumoto, Takayuki Gyohten, Tetsushi Tanizaki, Soichi Kobayashi, Masami Nakajima, Hiroyuki Yamasaki, Hideyuki Noda, Motoki Higashida, Yoshihiro Okuno, Kazutami Arimoto (Renesas) ICD2007-138		 This paper describes a real time image processing SoC(MX-SoC) with programmable multi matrix -processor(MX-Core) archite... [more] ICD2007-138
pp.107-111
CPSY 2007-10-25
13:00		 Kumamoto Kumamoto University The application of the massively parallel processor based on the matrix architecture
Katsuya Mizumoto, Hiroyuki Yamasaki, Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Masami Nakajima, Motoki Higashida, Yoshihiro Okuno, Kazutami Arimoto (Renesas) CPSY2007-24		 We have developed programmable matrix-processor "MX-1". The MX-1 consists of MX-Core and a control CPU. The MX-Core is a... [more] CPSY2007-24
pp.1-5
ICD, SDM 2006-08-17
09:05		 Hokkaido Hokkaido University A super parallel SIMD processor with Time/Space conversion Bus Bridge on the Matrix Architecture
Tetsushi Tanizaki, Takayuki Gyohten, Hideyuki Noda, Masami Nakajima, Katsuya Mizumoto, Katsumi Dosaka (Renesas) 		A super parallel SIMD processor based on the matrix architecture which consists of 2k processors, embedded SRAM, and tim... [more] SDM2006-125 ICD2006-79
pp.1-6
ICD 2006-05-25
13:00		 Hyogo Kobe University A 40GOPS 250mW Massively Parallel Processor Based on Matrix Architecture -- A Very High Performance Processor IP for Mobile System-on-Chips --
Kiyoshi Nakata, Masami Nakajima, Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten (Renesas) 		We have developed a massively parallel processor based on Matrix architecture. This architecture achieved 40GOPS of 16-b... [more] ICD2006-25
pp.19-23
 Results 1 - 4 of 4  /   
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