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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 17 of 17  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2022-11-30
09:55
Kumamoto  
(Primary: On-site, Secondary: Online)
Design of Digital Phase-Locked Loop Circuit based on 3rd-Order MASH ΔΣ FDC for Low In-Band Phase Noise
Ryoga Iwashita, Zule Xu, Masaru Osada, Ryoya Shibata, Yo Kumano, Tetsuya Iizuka (UTokyo) VLD2022-43 ICD2022-60 DC2022-59 RECONF2022-66
$DeltaSigma$ frequency-to-digital converter based phase locked loops (FDC-PLLs) can reduce its quantization noise at low... [more] VLD2022-43 ICD2022-60 DC2022-59 RECONF2022-66
pp.138-143
ICD, SDM, ITE-IST [detail] 2022-08-08
16:35
Online   [Invited Talk] A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur
Zule Xu, Masaru Osada, Tetsuya Iizuka (UTokyo) SDM2022-43 ICD2022-11
We present a type-II fractional-N hybrid switched-capacitor sampling PLL, using a capacitive digital-to-analog converter... [more] SDM2022-43 ICD2022-11
pp.41-44
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-15
16:10
Ehime Ehime Prefecture Gender Equality Center A 16 Gb/s Differential Transmitter With Far-End Crosstalk Cancellation Using Injection Timing Control
Daigo Takahashi (The Univ. of Tokyo), Yusuke Fujita, Satoshi Miura (THine Electronics), Tetsuya Iizuka (The Univ. of Tokyo) ICD2019-42 IE2019-48
This paper proposes a far-end crosstalk cancellation (FEXT) method with adjustable injection timing of the crosstalk can... [more] ICD2019-42 IE2019-48
pp.65-70
NLP 2019-05-11
13:25
Oita J:COM HoltoHALL OITA Design of parameters for chaotic synchronization in delayed-coupled Bernoulli maps with directed graph
Tetsuya Iizuka, Yoshiki Sugitani (Ibaraki Univ.) NLP2019-16
This study designs parameters to induce chaotic synchronization in delayed-coupled Bernolli maps with directed graph. Pr... [more] NLP2019-16
pp.87-91
ICD, CPSY, CAS 2018-12-23
09:30
Okinawa   [Poster Presentation] Design of 140GHz Area-and-Power-Efficient VCO using Frequency Doubler
Yoshitaka Otsuki, Daisuke Yamazaki, Nguyen Ngoc Mai-Khanh, Tetsuya Iizuka (Tokyo Univ.) CAS2018-98 ICD2018-82 CPSY2018-64
This report summarizes the design of a D-band VCO that realizes small area, low phase noise and low power consumption.
... [more]
CAS2018-98 ICD2018-82 CPSY2018-64
pp.83-88
ICD, CPSY, CAS 2017-12-14
09:50
Okinawa Art Hotel Ishigakijima Design of Quick-Lock Reference-Clock-Less All-Digital CDR using Delay Tunable Buffer for Lock Range Extension
Meikan Chin, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada (Univ. of Tokyo) CAS2017-64 ICD2017-52 CPSY2017-61
A quick-lock reference-clock-less all-digital burst-mode CDR is proposed. Since the proposed CDR resumes from a standby ... [more] CAS2017-64 ICD2017-52 CPSY2017-61
pp.3-8
ICD, CPSY, CAS 2017-12-14
10:10
Okinawa Art Hotel Ishigakijima Design of Non-Binary SAR ADC with Noise-Tunable Comparator
Takaaki Ito, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada (The Univ. of Tokyo) CAS2017-65 ICD2017-53 CPSY2017-62
A 16-bit non-binary SAR ADC with a noise-tunable comparator for low power consumption is presented. A non-binary-weight... [more] CAS2017-65 ICD2017-53 CPSY2017-62
pp.9-13
ICD, CPSY, CAS 2017-12-14
10:40
Okinawa Art Hotel Ishigakijima Performance Analysis of Level-Cross Detection Method based on Stochastic Comparator
Taiki Sugiyama, Tetsuya Iizuka (Univ. of Tokyo), Takahiro Yamaguchi (Advantest), Toru Nakura, Kunihiro Asada (Univ. of Tokyo) CAS2017-66 ICD2017-54 CPSY2017-63
ADC based on level-cross detection quantizes time rather than voltage. When the clock frequency is doubled, SNR of ADC i... [more] CAS2017-66 ICD2017-54 CPSY2017-63
pp.15-20
ICD, CPSY 2015-12-18
15:55
Kyoto Kyoto Institute of Technology Performance Analysis of Analog to Digital Converter Based on Stochastic Comparator
Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada (Tokyo University) ICD2015-93 CPSY2015-106
A performance model for Analog to Digital Converter (ADC) based on stochastic comparator has been proposed by analyzing ... [more] ICD2015-93 CPSY2015-106
pp.123-128
ICD, CPSY 2015-12-18
16:45
Kyoto Kyoto Institute of Technology Autonomously Tracking PVT Variations of Pulse Width Controlled PLL using Hill-Climbing Method
Toi Takashi, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada (Tokyo Univ.) ICD2015-95 CPSY2015-108
 [more] ICD2015-95 CPSY2015-108
pp.135-140
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-02
14:10
Nagasaki Nagasaki Kinro Fukushi Kaikan A Design of a Quick-Lock All-Digital CDR with Improved Jitter Performance by Fractional Phase Selection Technique
Norihito Tohge, Tetsuya Iizuka, Toru Nakura (Univ. of Tokyo), Satoshi Miura, Yoshimichi Murakami (THine), Kunihiro Asada (Univ. of Tokyo) CPM2015-130 ICD2015-55
A quick-lock all-digital Clock-Data Recovery circuit that does not require a reference clock is propposed. Internal
Tim... [more]
CPM2015-130 ICD2015-55
pp.17-22
ICD, IE, VLD, IPSJ-SLDM [detail] 2015-10-26
15:00
Miyagi   Design of Fine-Resolution Pulse Shrinking Time-to-Digital Converter
Takehisa Koga, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada (Univ. of Tokyo) VLD2015-29 ICD2015-42 IE2015-64
A pulse-shrinking Time-to-Digital Converter (TDC) with an offset pulse width detection scheme is presented. In the conve... [more] VLD2015-29 ICD2015-42 IE2015-64
pp.13-18
ICD, CPSY 2014-12-02
13:00
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Superliner or Cruiser -- For the Integrative and Disruptive Innovation --
Tetsuya Iizuka (THINE) ICD2014-104 CPSY2014-116
At the very begging time of the so-called Japan’s lost two decades plus, the author launched his own small business, a f... [more] ICD2014-104 CPSY2014-116
pp.115-120
ICD, CPSY 2014-12-02
16:05
Tokyo Kikai-Shinko-Kaikan Bldg. An accelerating method of NBTI degradation transition analysis based on logic simulation
Kazunori Mori, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada (UTokyo) ICD2014-109 CPSY2014-121
Negative Bias Temperature Instability (NBTI) degradation is one of the important problems in nano-scale transistors.In t... [more] ICD2014-109 CPSY2014-121
pp.141-145
ICD, ITE-IST 2011-07-22
09:25
Hiroshima Hiroshima Institute of Technology All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator
Tetsuya Iizuka, Kunihiro Asada (Univ. of Tokyo) ICD2011-26
This paper proposes an all-digital process variability monitor based on a shared structure of a buffer ring and a ring o... [more] ICD2011-26
pp.63-68
ICD, ITE-IST 2010-07-22
10:45
Osaka Josho Gakuen Osaka Center Buffer-Ring-Based All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Effect
Tetsuya Iizuka, Toru Nakura, Kunihiro Asada (Univ. of Tokyo) ICD2010-24
In this paper, we propose an all-digital process variability monitor which utilizes a simple buffer ring with a pulse co... [more] ICD2010-24
pp.15-20
VLD, ICD, DC, IPSJ-SLDM 2005-12-01
16:40
Fukuoka Kitakyushu International Conference Center Timing-Driven Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization
Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo)
 [more] VLD2005-74 ICD2005-169 DC2005-51
pp.79-84
 Results 1 - 17 of 17  /   
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