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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 16 of 16  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
IE, ITS, ITE-MMS, ITE-ME, ITE-AIT [detail] 2023-02-22
14:00
Hokkaido Hokkaido Univ. Hierarchical Minimum-Sized Object Detection Method using Clustering Algorithm for UAV Autonomus Flight
Yusei Horikawa, Makoto Sugaya, Tetsuya Matsumura (Nihon Univ)
 [more]
IE, ITS, ITE-MMS, ITE-ME, ITE-AIT [detail] 2023-02-22
11:30
Hokkaido Hokkaido Univ. A Study of Hierarchical Object Detection Method for Super High-Resolution Image Sensing
Makoto Sugaya, Yusei Horikawa, Renpei Yoshida, Tetsuya Matsumura (Nihon Univ.)
(To be available after the conference date) [more]
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2022-11-30
10:20
Ishikawa Kanazawa Bunka Hall
(Primary: On-site, Secondary: Online)
Deep Learning-based Hierarchical Object Detection System for High-Resolution Images
Yusei Horikawa, Makoto Sugaya, Renpei Yoshida, Kazuma Mashiko, Tetsuya Matsumura (Nihon Univ.) VLD2022-44 ICD2022-61 DC2022-60 RECONF2022-67
This paper describes a new deep learning-based hierarchical object detection algorithm for high-resolution vision sensor... [more] VLD2022-44 ICD2022-61 DC2022-60 RECONF2022-67
pp.144-149
IMQ, IE, MVE, CQ
(Joint) [detail]
2019-03-14
15:10
Kagoshima Kagoshima University Study of Ultra-low-latency Video Coding Method for Autonomous Vehicles
Kaito Mori, Seiji Mochizuki (Nihon Univ.), Kousuke Imamura, Koji Yogiashi, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.) IMQ2018-41 IE2018-125 MVE2018-72
Applications such as autonomous driving and virtual reality (VR) require low-latency transfer of high definition (HD) vi... [more] IMQ2018-41 IE2018-125 MVE2018-72
pp.109-114
CS 2018-07-13
10:30
Okinawa Eef Information Plaza (Kumejima Is.) A Study of Video-coding for Ultra-low Latency Network Transmission
Kaito Mori, Seiji Mochizuki (Nihon Univ.), Kousuke Imamura, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.) CS2018-37
Autonomous driving for vehicles and MR(Mixed Reality) for IoT(Internet of Things) equipment require ultra-low-latency vi... [more] CS2018-37
pp.121-126
VLD, HWS
(Joint)
2018-02-28
15:25
Okinawa Okinawa Seinen Kaikan Architecture of Full-HD 60-fps Real-time Optical Flow Processor
Satoshi Kanda (Nihon Univ.), Kousuke Imamura, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.) VLD2017-99
This paper describes the architecture design of Full-HD 60fps real-time optical flow processor. In this processor, the W... [more] VLD2017-99
pp.61-66
IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2018-01-19
10:40
Kanagawa Raiosha, Hiyoshi Campus, Keio University Design and Implementation of 176-MHz WXGA 30-fps Real-time Optical Flow Processor
Satoshi Kanda, Yu Suzuki, Masato Ito (Nihon Univ.), Kousuke Imamura, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.) VLD2017-79 CPSY2017-123 RECONF2017-67
This paper describes the design and implementation of a real-time optical flow processor using a single field-programmab... [more] VLD2017-79 CPSY2017-123 RECONF2017-67
pp.101-106
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-06
10:55
Kumamoto Kumamoto-Kenminkouryukan Parea Design Environment Construction for Three-Dimensional Sound Processor using High-Level Synthesis
Saya Ohira, Naoki Tsuchiya, Tetsuya Matsumura (Nihon Univ.) VLD2017-28 DC2017-34
A three-dimensional (3D) sound processor architecture that includes 3D sound processing intellectual property (IP) cores... [more] VLD2017-28 DC2017-34
pp.7-12
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-08
09:00
Kumamoto Kumamoto-Kenminkouryukan Parea A Packet Lookup Engine LSI with Automatic Rule Registration and Deletion Function
Yoshifumi Kawamura, Kousuke Imamura (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.), Yoshio Matsuda (Kanazawa Univ.) VLD2017-55 DC2017-61
 [more] VLD2017-55 DC2017-61
pp.171-176
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-28
14:15
Osaka Ritsumeikan University, Osaka Ibaraki Campus Design for 3-Demensional Sound Processor using a High-Level Synthesis
Saya Ohira, Naoki Tsuchiya, Tetsuya Matsumura (Nihon Univ.) RECONF2016-40
High quality sound systems are penetrated into our lifestyle in various fields. In recent years, Minimized audio spot ge... [more] RECONF2016-40
pp.1-6
VLD, CAS, MSS, SIP 2016-06-17
10:30
Aomori Hirosaki Shiritsu Kanko-kan An FPGA Implementation of Real-time Optical Flow Estimation Processor
Yu Suzuki, Masato Ito, Satoshi Kanda, Tetsuya Matsumura (Nihon Univ.), Kousuke Imamura, Yoshio Matsuda (Kanazawa Univ.) CAS2016-21 VLD2016-27 SIP2016-55 MSS2016-21
A real-time optical flow processor has been implemented using single FPGA chip. By introducing four effective methods, m... [more] CAS2016-21 VLD2016-27 SIP2016-55 MSS2016-21
pp.115-120
VLD 2016-03-01
09:00
Okinawa Okinawa Seinen Kaikan A Packet Lookup Engine LSI Based on Mismatch Detection and Hash Search
Yoshifumi Kawamura, Kousuke Imamura (Kanazawa Univ.), Naoki Miura, Masami Urano, Satoshi Shigematsu (NTT), Tetsuya Matsumura (Nihon Univ.), Yoshio Matsuda (Kanazawa Univ.) VLD2015-118
Developing an extremely efficient packet inspection algorithm for lookup engines is important to realize a high throughp... [more] VLD2015-118
pp.43-48
ICD, IE, VLD, IPSJ-SLDM [detail] 2015-10-26
16:15
Miyagi   A Design of the 178-MHz WXGA 30-fps Optical Flow Processor Based on HOE Algorithm
Tetsuya Matsumura (Nihon Univ.), Aoi Kurokawa, Kosuke Imamura, Yoshio Matsuda (Kanazawa Univ.) VLD2015-32 ICD2015-45 IE2015-67
We propose an optical flow processor, which allows real-time processing of WXGA 30-fps at 178.3 MHz. By introducing the ... [more] VLD2015-32 ICD2015-45 IE2015-67
pp.31-36
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-28
10:30
Oita B-ConPlaza The LSI Implementation of a Memory Based Field Programmable Device for MCU Peripherals
Yoshifumi Kawamura, Naoya Okada, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.), Hiroshi Makino (OIT), Kazutami Arimoto (Okayama Prefectural Univ.) VLD2014-108 DC2014-62
A Field Programmable Sequencer and Memory (FPSM), which is an embedded memory based programmable device for peripherals ... [more] VLD2014-108 DC2014-62
pp.239-244
IE, ICD, VLD, IPSJ-SLDM [detail] 2013-10-07
10:30
Aomori   A Memory Based Filed Programmable Device for Energy saving MCUs
Tetsuya Matsumura (Nihon Univ.), Yoshifumi Kawamura (Renesas Electronics), Naoya Okada (Kanazawa Univ.), Kazutami Arimoto (Okayama Prefectual Univ.), Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.) VLD2013-46 ICD2013-70 IE2013-46
A Field Programmable Sequencer and memory (FPSM), which is an embedded memory based programmable peripherals for Micro C... [more] VLD2013-46 ICD2013-70 IE2013-46
pp.1-6
SDM, ICD 2013-08-02
09:50
Ishikawa Kanazawa University A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry
Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Yuichiro Ishii (Renesas Electronics), Tetsuya Matsumura (Nihon Univ.), Yoshio Matsuda (Kanazawa Univ.) SDM2013-76 ICD2013-58
 [more] SDM2013-76 ICD2013-58
pp.53-57
 Results 1 - 16 of 16  /   
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