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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 20  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2022-11-28
13:05
Ishikawa Kanazawa Bunka Hall
(Primary: On-site, Secondary: Online)
Development of ASIC Prototype Chip Evaluation System using FPGA-SoM
Masashi Imai (Hirosaki Univ.), Kenji Kise (Tokyo Tech.), Tomohiro Yoneda (NII) VLD2022-19 ICD2022-36 DC2022-35 RECONF2022-42
An ASIC prototype chip requires the corresponding evaluation system based on its specification, resulting in lack of ver... [more] VLD2022-19 ICD2022-36 DC2022-35 RECONF2022-42
pp.1-6
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-23
14:45
Kanagawa Raiosha, Hiyoshi Campus, Keio University Study of a Simplified Digital Spiking Neuron and Its FPGA Implementation
Tomohiro Yoneda (NII) VLD2019-75 CPSY2019-73 RECONF2019-65
A simplified digital spiking neural network implementable on FPGAs is proposed in order to reduce necessary resources an... [more] VLD2019-75 CPSY2019-73 RECONF2019-65
pp.135-140
VLD, CAS, MSS, SIP 2016-06-17
15:50
Aomori Hirosaki Shiritsu Kanko-kan A Study on Fault Tolerant Features of Asynchronous Circuits using Voted-enable Latches
Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII) CAS2016-33 VLD2016-39 SIP2016-67 MSS2016-33
A bit flip caused by voltage fluctuation, soft errors, and hardware Trojans becomes one of serious issues in the modern ... [more] CAS2016-33 VLD2016-39 SIP2016-67 MSS2016-33
pp.179-184
VLD 2016-02-29
14:20
Okinawa Okinawa Seinen Kaikan Task Allocation Methods based on the Maximum Task Parallelism for Multi-core Systems with the DTTR Scheme
Hiroshi Saito (Univ. Aizu), Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII) VLD2015-113
In this paper, we propose a task allocation method for multi-core systems with the Duplication with
Temporary Triple Mo... [more]
VLD2015-113
pp.13-18
DC 2015-06-16
16:00
Tokyo Kikai-Shinko-Kaikan Bldg. Performance Evaluation of Dependability Improvement Methods for Multiple Core Systems based on Markov Models
Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII) DC2015-20
In embedded systems, multiple core system is a promising architecture not only for performance improvement, but also for... [more] DC2015-20
pp.25-30
CPSY, DC 2014-04-25
13:00
Tokyo   [Fellow Memorial Lecture] Synchronous Circuit Design vs. Asynchronous Circuit Design -- Trials to compare them from various aspects --
Tomohiro Yoneda (NII) CPSY2014-1 DC2014-1
In this talk, the asynchronous design, where execution is controlled in an event driven manner based on handshaking with... [more] CPSY2014-1 DC2014-1
p.1
CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] 2014-03-15
17:40
Okinawa   Developing an evaluation kit of a dependable NoC platform for automotive applications
Kazuki Nakai, Mutsuki Koizumi, Tomohiro Yoneda (NII) CPSY2013-105 DC2013-92
A centralized ECU (Electronic Control Unit), where a many-core system
functions as a set of several conventional automo... [more]
CPSY2013-105 DC2013-92
pp.133-138
IE, ICD, VLD, IPSJ-SLDM [detail] 2013-10-07
10:55
Aomori   Proposal of Double-clock and Dual-Edge-Triggered Flip-flops for Asynchronous Circuits
Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII) VLD2013-47 ICD2013-71 IE2013-47
There are mainly two types of handshaking protocols in asynchronous circuit design; 2-phase handshaking protocol and 4-p... [more] VLD2013-47 ICD2013-71 IE2013-47
pp.7-12
CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] 2013-03-14
14:30
Nagasaki   Towards Demonstration of a Dependable Network-on-Chip Platform for an Automotive Application
Kazuki Nakai, Chammika Mannakkara, Vijay Holimath, Tomohiro Yoneda (NII) CPSY2012-97 DC2012-103
A centralized ECU (Electronic Control Unit), where a many-core system
functions as a set of several conventional autom... [more]
CPSY2012-97 DC2012-103
pp.271-276
VLD 2013-03-05
11:15
Okinawa Okinawa Seinen Kaikan A Multi-Task Scheduling and Allocation for Highly Reliable Network-on-Chip
Hiroshi Saito (Univ. of Aizu), Tomohiro Yoneda (NII), Yuichi Nakamura (NEC) VLD2012-146
 [more] VLD2012-146
pp.61-66
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2011-11-29
13:25
Miyazaki NewWelCity Miyazaki An Integer Linear Programming based Multiple Task Allocation Method for Fault Tolerance in Network on Chip
Hiroshi Saito (Univ. Aizu), Tomohiro Yoneda (NII), Yuichi Nakamura (NEC) VLD2011-77 DC2011-53
This paper proposes a multiple task allocation method for given NoC model, task graph, and the number of expected failur... [more] VLD2011-77 DC2011-53
pp.147-152
DC 2011-10-20
15:10
Tokyo   An Online Routing Mechanism with Higher Fault-Tolerance for Network-on-Chip
Daihan Wang, Chammika Mannakkara, Vijay Holimath, Tomohiro Yoneda (NII) DC2011-26
In this work we present an idea of a new online fault-tolerant routing mechanism for Network-on-Chip (NoC).
Compared wi... [more]
DC2011-26
pp.37-42
DC, CPSY 2011-04-12
13:50
Tokyo   A Case Study on Dependable Network-on-Chip Platform for Automotive Applications
Chammika Mannakkara, Daihan Wang, Vijay Holimath, Tomohiro Yoneda (NII) CPSY2011-3 DC2011-3
This report presents our first trial to apply a Network-on-Chip (NoC)
architecture to a gasoline engine control, one of... [more]
CPSY2011-3 DC2011-3
pp.11-16
DC, CPSY 2010-04-13
13:30
Tokyo   [Invited Talk] Increasing Dependability based on Asynchronous Computation
Tomohiro Yoneda (NII/Tokyo Tech.) CPSY2010-1 DC2010-1
As semiconductor process technology scales and device dimensions shrink, new types of faults, such as slow transistors d... [more] CPSY2010-1 DC2010-1
p.1
CPSY, DC
(Joint)
2009-08-04
- 2009-08-05
Miyagi   A robust on-chip asynchronous data-transfer scheme based on multi-level current-mode signalling
Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu (Tohoku Univ.), Tomohiro Yoneda (NII) DC2009-18
This paper presents a robust on-chip asynchronous data-trasnfer circuit based on multi-level current-mode signalling und... [more] DC2009-18
pp.1-6
DC, CPSY 2008-04-23
16:45
Tokyo Tokyo Univ. An approach to tolerating delay faults based on asynchronous circuits
Tomohiro Yoneda (NII), Masashi Imai (Univ. of Tokyo), Atsushi Matsumoto, Takahiro Hanyu (Tohoku Univ.), Yuichi Nakamura (NEC) CPSY2008-10 DC2008-10
Recent advances in semiconductor process technologies cause new types of faults, which should be handled in order to obt... [more] CPSY2008-10 DC2008-10
pp.55-60
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2007-11-20
15:10
Fukuoka Kitakyushu International Conference Center Comparison of Standard Cell Non-linear Asynchronous Pipelines
Chammika Mannakkara, Tomohiro Yoneda (NII) VLD2007-78 DC2007-33
Two types of non-linear asynchronous pipeline constructs, namely Conditional Branch and Asynchronous were compared for 2... [more] VLD2007-78 DC2007-33
pp.49-54
RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2006-11-28
16:10
Fukuoka Kitakyushu International Conference Center Proposal of a Behavioral Synthesis Method for Asynchronous Circuits in Bundled-data Implementation
Naohiro Hamada, Takao Konishi, Hiroshi Saito (The Univ. of Aizu), Tomohiro Yoneda (NII), Takashi Nanya (The Univ. of Tokyo)
 [more] VLD2006-63 DC2006-50
pp.71-76
CPSY, DC 2006-04-14
11:10
Tokyo Takeda Hall Hazard Checking of Asynchronous Circuits: A New Approach
Frederic Beal (Tokyo Inst. of Tech.), Tomohiro Yoneda (NII), Chris Myers (Univ. of Utah)
We present a new framework to express the semantics of asynchronous
circuits, and as an application, an algorithm that ... [more]
CPSY2006-5 DC2006-5
pp.25-30
VLD, ICD, DC, IPSJ-SLDM 2005-12-02
15:25
Fukuoka Kitakyushu International Conference Center Efficient contraction of timed signal transition graphs
Tomohiro Yoneda (NII), Chris Myers (Univ. of Utah)
In the decomposition based synthesis method, for each output signal,
an input signal set sufficient to synthesize a cir... [more]
VLD2005-86 ICD2005-181 DC2005-63
pp.59-64
 Results 1 - 20 of 20  /   
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