IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 5 of 5  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2013-03-06
13:40
Okinawa Okinawa Seinen Kaikan A Delay Control Circuit with Channel Length Decomposition and Its Application
Yuichi Toyota, Yuki Nakashima, Toru Fujimura, Shigetoshi Nakatake (Univ of Kitakyushu) VLD2012-158
In recent years, as the progress of the semiconductor manufacturing, the variations of circuit performance due to device... [more] VLD2012-158
pp.123-128
VLD 2011-03-04
11:15
Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center On Realization and Evaluation of Capacitors in Analog Integrated Circuits
Atsushi Ochi, Ryoei Shimazu, Toru Fujimura, Shigetoshi Nakatake (Univ.of Kitakyushu) VLD2010-140
As proceeding to a deep submicron era,
the area efficiency of and the precision of passive components have become
impo... [more]
VLD2010-140
pp.141-146
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-04
10:40
Kochi Kochi City Culture-Plaza Transistor-Array-Based Opamp Layout and its Evaluationon
Arisa Kawazoe, Toru Fujimura, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2009-60 DC2009-47
This paper proposes
a novel MOS analog design style along with layout automation,
called Transistor-Array (TA),
whi... [more]
VLD2009-60 DC2009-47
pp.131-136
VLD, ICD 2008-03-05
15:45
Okinawa TiRuRu MOS Analog Module Generation
Akio Fujii, Takehiko Matsuo, Toru Fujimura, Bo Yang, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2007-143 ICD2007-166
This paper addresses the module layout configuration issue of MOS analog LSI. We notice that the key characteristic of t... [more] VLD2007-143 ICD2007-166
pp.37-42
ICD, VLD 2007-03-08
16:10
Okinawa Mielparque Okinawa Programmable CMOS Analog Circuit with Body Biasing
Youhei Ide, Toru Fujimura, Shinya Takeshita, Masatoshi Nakamura, Shigetoshi Nakatake (Univ. of Kitakyushu)
 [more] VLD2006-137 ICD2006-228
pp.109-114
 Results 1 - 5 of 5  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan