| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CPSY, DC, IPSJ-ARC [detail] | 2023-08-03 10:55 |
Hokkaido | Hakodate Arena (Primary: On-site, Secondary: Online) |
An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing Yudai Toyooka, Haruki Watanabe, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ)  CPSY2023-11 DC2023-11 |
[more] | CPSY2023-11 DC2023-11 pp.19-24 |
| CPSY, DC, IPSJ-ARC [detail] | 2023-08-03 11:20 |
Hokkaido | Hakodate Arena (Primary: On-site, Secondary: Online) |
A Don't Care Filling Method of Control Signals in Controllers to Maximize the Number of Distinguishable Weighted Hardware Element Pairs Yui Otsuka, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.), Koji Yamazaki (Meiji Univ.) CPSY2023-12 DC2023-12 |
[more] | CPSY2023-12 DC2023-12 pp.25-30 |
| HWS, VLD | 2023-03-03 11:50 |
Okinawa | (Primary: On-site, Secondary: Online) |
A Seed Selection Method to Minimize Test Application Time for Logic BIST Using Pseudo Boolean Optimization Rei Miura, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.) VLD2022-105 HWS2022-76 |
[more] | VLD2022-105 HWS2022-76 pp.173-178 |
| HWS, VLD | 2023-03-03 13:50 |
Okinawa | (Primary: On-site, Secondary: Online) |
A Logic Locking Method based on Function Modification Circuit Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Rei Miura, Toshinori Hosokawa (Nihon Univ.) VLD2022-107 HWS2022-78 |
In recent years, with the increase of VLSI integration, semiconductor design companies to design a VLSI have tended to u... [more] | VLD2022-107 HWS2022-78 pp.185-190 |
| DC | 2023-02-28 11:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg (Primary: On-site, Secondary: Online) |
A Test Generation Method to Distinguish Multiple Fault Pairs for Improvement of Fault Diagnosis Resolution Yuya Chida, Toshinori Hosokawa (NIhon Univ.), Koji Yamazaki (Meiji Univ.) DC2022-83 |
(To be available after the conference date) [more] | DC2022-83 pp.6-11 |
| DC | 2023-02-28 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg (Primary: On-site, Secondary: Online) |
A Seed Generation Method for Multiple Random Pattern Resistant Transition Faults for BIST Yangling Xu, Rei Miura, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (KSU) DC2022-89 |
With shrinking feature sizes, growing clock frequencies, and decreasing power supply voltage, modern very large integrat... [more] | DC2022-89 pp.39-44 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-29 09:15 |
Kumamoto | (Primary: On-site, Secondary: Online) |
A Don't Care Filling Method of control signals for controllers to Maximize the Number of Distinguishable Hard ware Element Pairs Yui Otsuka, Yuya Chida, Xu Haofeng, Toshinori Hosokawa (Nihon Univ.), Kouji Yamazaki (Meiji Univ.) VLD2022-25 ICD2022-42 DC2022-41 RECONF2022-48 |
[more] | VLD2022-25 ICD2022-42 DC2022-41 RECONF2022-48 pp.37-42 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-29 09:40 |
Kumamoto | (Primary: On-site, Secondary: Online) |
Test Generation Merhod based on RTL Design for Diagnosability Yuya Chida, Toshinori Hosokawa (Nihon univ.), Koji Yamazaki (Meiji Univ.) VLD2022-26 ICD2022-43 DC2022-42 RECONF2022-49 |
(To be available after the conference date) [more] | VLD2022-26 ICD2022-43 DC2022-42 RECONF2022-49 pp.43-48 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-29 10:05 |
Kumamoto | (Primary: On-site, Secondary: Online) |
A Seed Generation Method for Multiple Random Pattern Resistant Stuck-at Faults in Built-In Self-Test Rei Miura, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.) VLD2022-27 ICD2022-44 DC2022-43 RECONF2022-50 |
[more] | VLD2022-27 ICD2022-44 DC2022-43 RECONF2022-50 pp.49-54 |
| CPSY, DC, IPSJ-ARC [detail] | 2022-07-27 09:45 |
Yamaguchi | Kaikyo Messe Shimonoseki (Primary: On-site, Secondary: Online) |
Enrei Jo, Rei Miura, Toshinori Hosokawa (Nihon Univ), Masayosi Yoshimura (KSU) CPSY2022-1 DC2022-1 |
In recent years, with the low power design of VLSIs, many low power oriented don't care (X) identification methods and X... [more] | CPSY2022-1 DC2022-1 pp.1-6 |
| CPSY, DC, IPSJ-ARC [detail] | 2022-07-27 10:15 |
Yamaguchi | Kaikyo Messe Shimonoseki (Primary: On-site, Secondary: Online) |
Faster low-power oriented test generation methods using fault excitation conditions Rei Miura, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.), Masayuki Arai (Nihon Univ.) CPSY2022-2 DC2022-2 |
[more] | CPSY2022-2 DC2022-2 pp.7-12 |
| CPSY, DC, IPSJ-ARC [detail] | 2022-07-27 11:00 |
Yamaguchi | Kaikyo Messe Shimonoseki (Primary: On-site, Secondary: Online) |
A Block Partitioning Method to Accelerate Test Generation for Gate-Exhaustive Faults Momona Mizota, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.) CPSY2022-3 DC2022-3 |
In gate-exhaustive fault model which covers defects in cells, since the number of faults is proportion to that of gates,... [more] | CPSY2022-3 DC2022-3 pp.13-18 |
| CPSY, DC, IPSJ-ARC [detail] | 2022-07-27 11:30 |
Yamaguchi | Kaikyo Messe Shimonoseki (Primary: On-site, Secondary: Online) |
Field Testability Evaluation Using State Signal Sequences Based on k-Consecutive State Transitions for Field Testing Yudai Toyooka, Yuki Watanabe, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) CPSY2022-4 DC2022-4 |
[more] | CPSY2022-4 DC2022-4 pp.19-24 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2022-03-10 10:30 |
Online | Online | A Don't Care Filling Method of Control Signals for Concurrent Logical Fault Testing Haofeng Xu, Toshinori Hosokawa, Hiroshi Yamazaki, Masayuki Arai (Nihon Univ), Masayoshi Yoshimura (KSU) CPSY2021-56 DC2021-90 |
In recent years, with the increase in test cost for VLSIs, it has been important to reduce the number of test patterns. ... [more] | CPSY2021-56 DC2021-90 pp.67-72 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2022-03-10 10:50 |
Online | Online | A Test Generatoin Method to Improve Diagonostic Resolution Based on Fault Sensitization Coverage Yuya Chida, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.) CPSY2021-57 DC2021-91 |
As one of test generation methods to achieve high defect coverage, n-detection test generation methods have been propose... [more] | CPSY2021-57 DC2021-91 pp.73-78 |
| DC | 2022-03-01 13:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
A Logic Locking Method based on SFLL-hd at Register Transfer Level Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.) DC2021-72 |
In recent years, with the increase of VLSI integration, LSI design companies utilize circuit design information, called ... [more] | DC2021-72 pp.45-50 |
| DC | 2022-03-01 15:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
State assignment method to improve transition fault coverage for controllers including invalid states Kyohei Iizuka, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ) DC2021-75 |
[more] | DC2021-75 pp.63-68 |
| DC | 2022-03-01 15:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
Evaluation of Don't Care Filling Method of Control Signals to Enhance Fault Diagnosability for Logic and Timing Fault Kohei Tsuchibuchi, Xu Haofeng, Yuya Chida, Toshinori Hosokawa (Nihon Univ), Koji Yamazaki (Meiji Univ) DC2021-76 |
[more] | DC2021-76 pp.69-74 |
| DC | 2022-03-01 16:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
An Estimation Method of Defect Types for Multi-cycle Capture Testing Using Artificial Neural Networks and Fault Detection Information Natsuki Ota, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.), Masayuki Arai, Yukari Yamauchi (Nihon Univ.) DC2021-77 |
[more] | DC2021-77 pp.75-80 |
| DC | 2021-12-10 13:00 |
Kagawa | (Primary: On-site, Secondary: Online) |
A Low Power Oriented Multiple Target Test Generation Method Rei Miura, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.), Masayuki Arai (Nihon Univ.) DC2021-55 |
In recent years, since capture power consumption for VLSIs significantly increases in at-speed scan testing, low capture... [more] | DC2021-55 pp.1-6 |
[Return to Top Page]