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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2019-05-09 16:35 |
Tokyo | Tokyo Tech Front (Tokyo) | A case study of an FPGA implementation for streaming data filtering Hiroki Nakagawa, Yasutaka TsuTsumi, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)  RECONF2019-8 |
With the spread of IoT (Internet of Things) equipment in recent years, collection of big data becomes easy, and the dema... [more] | RECONF2019-8 pp.41-46 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 09:00 |
Hiroshima | Satellite Campus Hiroshima (Hiroshima) | Resources Utilization of Fine-grained Overlay Architecture Theingi Myint (Kumamoto), Qian Zhao (Kyutech), Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto) RECONF2018-37 |
This paper focuses on utilization of hardware resources for fine-grained overlay architecture. Overlay architectures inc... [more] | RECONF2018-37 pp.15-20 |
| RECONF | 2018-09-17 14:30 |
Fukuoka | LINE Fukuoka Cafe Space (Fukuoka) | A Case Study on Complex Event Processing over low cost ARM+FPGA Boards. Hendarmawan (Kumamoto University), Qian Zhao (Kyutech), Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto University) RECONF2018-21 |
[more] | RECONF2018-21 pp.13-18 |
| RECONF | 2018-09-18 15:15 |
Fukuoka | LINE Fukuoka Cafe Space (Fukuoka) | A case study of database filtering on streaming processing Hiroki Nakagawa, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2018-33 |
With the spread of IoT (Internet of Things) equipment in recent years, collection of big data becomes easy, and the dema... [more] | RECONF2018-33 pp.79-84 |
| RECONF | 2018-05-24 14:30 |
Tokyo | GATE CITY OHSAKI (Tokyo) | Visibility study of CNN implementation using High Speed Serial Optical Interconnection Juntaro Chikama, Yasuhiro Nakahara, Motoki Amagasaki, Morihiro Kuga, Msahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2018-7 |
In this research, we realize a low power consumption and scalable system by implementing CNN on multi FPGA system.To sol... [more] | RECONF2018-7 pp.33-38 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-19 13:00 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Kanagawa) | FPGA accelerator of CNN using Power of 2 Approximation and Pruning weights Takahiro Utsunomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2017-82 CPSY2017-126 RECONF2017-70 |
Convolutional Neural Network (CNN), a method of Image recognition, is utilized in various fields. Field Programmable Gat... [more] | VLD2017-82 CPSY2017-126 RECONF2017-70 pp.119-124 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 10:30 |
Kumamoto | Kumamoto-Kenminkouryukan Parea (Kumamoto) | hCODE 2.0: An Open-source Platform for FPGA Cluster System Hiroki Nakagawa, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2017-27 DC2017-33 |
In recent years, major cloud providers such as Amazon and Microsoft are improving cloud applications using FPGAs. By in... [more] |
VLD2017-27 DC2017-33 pp.1-6 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 13:25 |
Kumamoto | Kumamoto-Kenminkouryukan Parea (Kumamoto) | RECONF2017-38 |
Graph processing has memory access with low locality, and it is not easy to process large-scale graphs which have the mi... [more] | RECONF2017-38 pp.7-12 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 09:50 |
Kumamoto | Kumamoto-Kenminkouryukan Parea (Kumamoto) | Performance Evaluation Three Dimensional FPGA Architecture with Face-down Stacking Keishiro Akashi, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ) RECONF2017-42 |
In recent years,Three-dimensional (3D) field-programmable gate arrays(FPGAs) are expected to offer higher logic density ... [more] | RECONF2017-42 pp.31-36 |
| RECONF | 2017-09-26 13:55 |
Tokyo | DWANGO Co., Ltd. (Tokyo) | A case study of High-level Synthesis Using Higher-order Function on Functional Language Takuya Teraoka, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2017-35 |
The growing capabilities of silicon technology and the increasing complexity of applications in recent decades have forc... [more] | RECONF2017-35 pp.75-80 |
| RECONF, CPSY, DC, IPSJ-ARC (Joint) [detail] |
2017-05-22 16:20 |
Hokkaido | Noboribetsu-Onsen Dai-ichi-Takimoto-Kan (Hokkaido) | CNN implementation on FPGA with Power of 2 Approximation of Weight Takahiro Utsunomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2017-6 |
Convolutional Neural Network (CNN), a method of Image recognition, is utilized in various fields. Considering CNN implem... [more] | RECONF2017-6 pp.25-30 |
| RECONF, CPSY, DC, IPSJ-ARC (Joint) [detail] |
2017-05-22 17:10 |
Hokkaido | Noboribetsu-Onsen Dai-ichi-Takimoto-Kan (Hokkaido) | A proposal of Bit Serial Arithmetic Units for Arbitrary Precision Tomonori Miura, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2017-8 |
In this paper,we propose a bit serial arithmetic unit for arbitrary precision.It calculates 1 digit ev- ery cycle from t... [more] | RECONF2017-8 pp.37-41 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-23 15:20 |
Kanagawa | Hiyoshi Campus, Keio Univ. (Kanagawa) | Implementation of Multiple FPGAs with High Speed Serial Optical Interconnection Futoshi Murase, Daichi Takagi, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ) VLD2016-75 CPSY2016-111 RECONF2016-56 |
We propose a multiple FPGA system using high speed optical serial interconnection for a inter-connection of FPGAs. In th... [more] | VLD2016-75 CPSY2016-111 RECONF2016-56 pp.31-36 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 10:55 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus (Osaka) | Development of power estimation tool for three dimensional FPGA Masato Ikebe, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2016-46 |
Three-dimensional (3D) stacking technology is attractive for providing another way to improve the performance of the lar... [more] | RECONF2016-46 pp.35-40 |
| MSS, CAS, IPSJ-AL [detail] | 2016-11-25 12:55 |
Hyogo | Kobe Institute of Computing (Hyogo) | Formal Description of Synchronization by Functional Definition of Synchronous Circuits Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ.) CAS2016-73 MSS2016-53 |
Synchronous circuits are usually defined as D-Flipflop (D-FF) synchronized circuits, but it is doubtful that D-FF comple... [more] | CAS2016-73 MSS2016-53 pp.99-104 |
| RECONF | 2016-09-06 10:55 |
Toyama | Univ. of Toyama (Toyama) | A Study of Methodology and Tools for Open-source FPGA Accelerators Takuya Nakamichi, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2016-34 |
Today's information and communication society requires more and higher-performance computing devices with the constraint... [more] | RECONF2016-34 pp.45-50 |
| VLD, IPSJ-SLDM | 2016-05-11 13:50 |
Fukuoka | Kitakyushu International Conference Center (Fukuoka) | Multi bit soft error tolerant FPGA architecture Yuji Nakamura, Takuya Teraoka, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2016-3 |
Due to reaching the nanoscale transistor size, effect of soft error to the memory has become conspicuous. In small devic... [more] | VLD2016-3 pp.35-40 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-19 11:05 |
Kanagawa | Hiyoshi Campus, Keio University (Kanagawa) | FPGA routing structure based on H-Tree topology Yuki ishii, Masato Ikebe, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2015-78 CPSY2015-110 RECONF2015-60 |
FPGA(Fiele Programmable Gate Array) has many routing resources in order to provide the flexibility. These routing resour... [more] | VLD2015-78 CPSY2015-110 RECONF2015-60 pp.7-12 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 11:15 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan (Nagasaki) | A Study of HW/SW Co-design Framework based on the Virtualization Technology Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2015-52 |
One challenge for the heterogeneous computing with the FPGA is to bridge the development gap between SW and HW design. T... [more] | RECONF2015-52 pp.21-26 |
| RECONF | 2015-09-18 09:25 |
Ehime | Ehime University (Ehime) | Trax solver based on machine-learned evaluation function Takuya Nakamichi, Yusuke Sonoda, Takayuki Matsuzaki, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2015-33 |
We develop a solver of board game Trax. Our basic strategy is a common game tree search algorithm. We explore the best m... [more] | RECONF2015-33 pp.7-12 |
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