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Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY 2008-12-18
16:10		 Kyoto KYOTO Research Park An Architecture of Dynamically Reconfigurable Systolic Array and FPGA Implementation
Toshiyuki Ishimura, Yuhki Hayakawa, Akinori Kanasugi (Tokyo Denki Univ.) CPSY2008-52		 The dynamically reconfigurable processors which have high-speed performance of ASIC, flexibility of FPGA and high area e... [more] CPSY2008-52
pp.55-60
SIS 2008-03-13
11:15		 Tokyo Musashi Institute of Technology(Setagaya) An Architecture of Dynamically Reconfigurable Systolic Array
Toshiyuki Ishimura, Akinori Kanasugi (TDU) SIS2007-70		 The Dynamically Reconfigurable Device which has high-speed performance of ASIC, flexibility of FPGA and high area effici... [more] SIS2007-70
pp.11-16
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