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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-29
09:05
Kanagawa   Evaluation of a Multicore Reconfigurable Architecture
Vu Manh Tuan, Hiroki Matsutani, Naohiro Katsura, Hideharu Amano (Keio Univ.) VLD2008-92 CPSY2008-54 RECONF2008-56
A multicore reconfigurable architecture consisting of multiple small computational cores connected by an interconnection... [more] VLD2008-92 CPSY2008-54 RECONF2008-56
pp.7-12
RECONF, CPSY, VLD, IPSJ-SLDM 2008-01-17
15:00
Kanagawa Hiyoshi Campus, Keio University A Method for Saving and Restoring Context Data of Hardware Tasks on the Dynamically Reconfigurable Processor
Vu Manh Tuan, Hideharu Amano (Keio Univ.) VLD2007-130 CPSY2007-73 RECONF2007-76
 [more] VLD2007-130 CPSY2007-73 RECONF2007-76
pp.71-76
RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2006-11-30
14:20
Fukuoka Kitakyushu International Conference Center Performance Evaluation of Multi-core DRP for Stream Application
Naohiro Katsura, Yohei Hasegawa, Vu Manh Tuan, Hiroki Matsutani, Hideharu Amano (Keio Univ.)
 [more] RECONF2006-52
pp.49-54
RECONF 2006-09-15
11:15
Kumamoto Kumamoto Univ. PERFORMANCE EVALUATION OF HARDWARE MULTI-PROCESS EXECUTION ON THE DYNAMICALLY RECONFIGURABLE PROCESSOR
Vu Manh Tuan, Yohei Hasegawa, Naohiro Katsura, Hideharu Amano (Keio Univ.)
The hardware multi-process execution is a technique to enhance throughput by dividing reconfigurable devices into severa... [more] RECONF2006-31
pp.25-30
RECONF, CPSY, VLD, IPSJ-SLDM 2006-01-17
15:25
Kanagawa   Implementation of Stream Application on Programmable Devices by C Level Design
Naohiro Katsura, Yohei Hasegawa, Vu Manh Tuan, Takamasa Kanamori, Hideharu Amano (Keio Univ.)
While FPGA is a fine grain composition, the Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a... [more] VLD2005-93 CPSY2005-49 RECONF2005-82
pp.31-36
RECONF 2005-09-15
14:00
Hiroshima   Performance and Power Analysis of Time-multiplexed Execution on Dynamically Reconfigurable Processor
Yohei Hasegawa, Hideharu Amano, Shohei Abe, Shunsuke Kurotaki, Vu Manh Tuan (Keio Univ.)
Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that ... [more] RECONF2005-35
pp.31-36
 Results 1 - 6 of 6  /   
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