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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 15 of 15  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, SDM, ITE-IST [detail] 2020-08-07
Online Online [Invited Talk] Understanding the Origin of Low-frequency Noise in Cryo-CMOS Toward Long-coherence-time Si Spin Qubit
Hiroshi Oka, Takashi Matsukawa, Kimihiko Kato, Shota Iizuka, Wataru Mizubayashi, Kazuhiko Endo, Tetsuji Yasuda, Takahiro Mori (AIST) SDM2020-6 ICD2020-6
Si quantum computer has attracted a significant attention due to its potential for large-scale integration using semicon... [more] SDM2020-6 ICD2020-6
SDM 2017-01-30
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Demonstrating Performance Improvement of Complementary TFET Circuits by ION Enhancement Based on Isoelectronic Trap Technology
Takahiro Mori, Hidehiro Asai, Junichi Hattori, Koichi Fukuda, Shintaro Otsuka, Yukinori Morita, Shin-ichi O'uchi, Hiroshi Fuketa, Shinji Migita, Wataru Mizubayashi, Hiroyuki Ota, Takashi Matuskawa (ANational Institute of Advanced Industrial ScieIST) SDM2016-130
We improved the performance of a complementary circuit comprising Si-based tunnel field-effect transistors (TFETs) by us... [more] SDM2016-130
SDM 2016-01-28
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Understanding of BTI for Tunnel FETs
Wataru Mizubayashi, Takahiro Mori, Koichi Fukuda, Yuki Ishikawa, Yukinori Morita, Shinji Migita, Hiroyuki Ota, Yongxun Liu, Shinichi O'uchi, Junichi Tsukada, Hiromi Yamauchi, Takashi Matsukawa, Meishoku Masahara, Kazuhiko Endo (AIST) SDM2015-122
(To be available after the conference date) [more] SDM2015-122
SDM 2015-01-27
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Accurate Prediction of PBTI Lifetime in N-type Fin-Channel High-k Tunnel FETs
Wataru Mizubayashi, Takahiro Mori, Koichi Fukuda, Yongxun Liu, Takashi Matsukawa, Yuki Ishikawa, Kazuhiko Endo, Shinichi Ohuchi, Junichi Tsukada, Hiromi Yamauchi, Yukinori Morita, Shinji Migita, Hiroyuki Ota, Meishoku Masahara (AIST) SDM2014-143
The positive bias temperature instability (PBTI) characteristics for n-type fin-channel tunnel FETs (TFETs) with high-k ... [more] SDM2014-143
SDM 2015-01-27
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Scaling Breakthrough for Analog/Digital Circuits by Suppressing Variability and Low-Frequency Noise for FinFETs by Amorphous Metal Gate Technology
Takashi Matsukawa, Koichi Fukuda, Yongxun Liu, Junichi Tsukada, Hiromi Yamauchi, Yuki Ishikawa, Kazuhiko Endo, Shinichi O'uchi, Shinji Migita, Wataru Mizubayashi, Yukinori Morita, Hiroyuki Ota, Meishoku Masahara (AIST) SDM2014-145
 [more] SDM2014-145
SDM 2015-01-27
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Experimental Realization of Complementary p- and n- Tunnel FinFETs with Subthreshold Slopes of Less than 60 mV/decade and Very Low (pA/um) Off-Current on a Si CMOS Platform
Yukinori Morita, Takahiro Mori, Koichi Fukuda, Wataru Mizubayashi, Shinji Migita, Takashi Matsukawa, Kazuhiko Endo, Shinichi O'uchi, Yongxun Liu, Meishoku Masahara, Hiroyuki Ota (AIST) SDM2014-146
Complementary (p- and n-type) tunnel FinFETs operating with subthreshold slopes (SSs) of less than 60 mV/decade and very... [more] SDM2014-146
ICD, SDM 2014-08-04
Hokkaido Hokkaido Univ., Multimedia Education Bldg. [Invited Talk] Research progress in steep slope devices and technologies to enhance ON current in TFETs
Takahiro Mori, Yukinori Morita, Shinji Migita, Wataru Mizubayashi, Koichi Fukuda, Noriyuki Miyata, Tetsuji Yasuda, Meishoku Masahara, Hiroyuki Ota (AIST) SDM2014-67 ICD2014-36
Steep slope devices (SSDs) have attracted because of the increase demand for low-power devices. This paper reviews recen... [more] SDM2014-67 ICD2014-36
ICD 2014-04-18
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Multigate FinFET Device and Circuit Technology for 10nm and Beyond
Meishoku Masahara, Kazuhiko Endo, Shin-ichi Ouchi, Takashi Matsukawa, Yongxun Liu, Shinji Migita, Wataru Mizubayashi, Yukinori Morita, Hiroyuki Ota (AIST) ICD2014-15
One of the biggest challenges for the VLSI circuits with 20-nm-technology nodes and beyond is to overcome the issue of a... [more] ICD2014-15
SDM 2014-01-29
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Heated Ion Implantation Technology for Highly Reliable Metal-gate/High-k CMOS SOI FinFETs
Wataru Mizubayashi (AIST), Hiroshi Onoda, Yoshiki Nakashima (Nissin Ion Equipment), Yuki Ishikawa, Takashi Matsukawa, Kazuhiko Endo, Yongxun Liu, Shinichi Ouchi, Junichi Tsukada, Hiromi Yamauchi, Shinji Migita, Yukinori Morita, Hiroyuki Ota, Meishoku Masahara (AIST) SDM2013-138
The impact of heated ion implantation (I/I) technology on metal-gate (MG)/high-k (HK) CMOS SOI FinFET performance and re... [more] SDM2013-138
SDM, ICD 2013-08-01
Ishikawa Kanazawa University Performance Enhancement of Tunnel Field-Effect Transistors by Synthetic Electric Field Effect
Yukinori Morita, Takahiro Mori, Shinji Migita, Wataru Mizubayashi, Akihito Tanabe, Koichi Fukuda, Kazuhiko Endo, Takashi Matsukawa, Shin-ichi O'uchi, Yongxun Liu, Meishoku Masahara, Hiroyuki Ota (AIST) SDM2013-66 ICD2013-48
A synthetic electric field effect to enhance the performance of tunnel field-effect transistors (TFETs) is proposed. The... [more] SDM2013-66 ICD2013-48
SDM 2012-11-16
Tokyo Kikai-Shinko-Kaikan Bldg Nonlocal band to band tunneling model for tunnel-FETs -- Device and circuit models --
Koichi Fukuda, Takahiro Mori, Wataru Mizubayashi, Yukinori Morita, Akihito Tanabe, Meishoku Masahara, Tetsuji Yasuda, Shinji Migita, Hiroyuki Ota (AIST) SDM2012-111
Device and compact models for tunnel-FETs are developed based on nonlocal band to band tunneling model. For device model... [more] SDM2012-111
SDM 2012-06-21
Aichi VBL, Nagoya Univ. Schottky Barrier Height Lowering by Dopant Segregation and Exact Control of Junction Position in Epitaxial NiSi2 Source/Drain
Wataru Mizubayashi, Shinji Migita, Yukinori Morita, Hiroyuki Ota (AIST) SDM2012-57
 [more] SDM2012-57
SDM 2009-06-19
Tokyo An401・402 Inst. Indus. Sci., The Univ. of Tokyo Electrical Properties of Ge MIS Interface Defects
Noriyuki Taoka, Wataru Mizubayashi, Yukinori Morita, Shinji Migita, Hiroyuki Ota (MIRAI-NIRC), Shinichi Takagi (MIRAI-NIRC/Univ. of Tokyo) SDM2009-30
The response of majority and minority carriers with interface traps have been systematically investigated for Ge MIS int... [more] SDM2009-30
SDM 2008-06-10
Tokyo An401・402, Inst. Indus. Sci., The Univ. of Tokyo The role of the high-k/SiO2 interface in the control of the threshold voltage for high-k MOS devices
Kunihiko Iwamoto, Yuuichi Kamimuta (MIRAI-ASET), Yu Nunoshige (Shibaura Institute of Technology), Akito Hirano, Arito Ogawa, Yukimune Watanabe (MIRAI-ASET), Shinji Migita, Wataru Mizubayashi, Yukinori Morita (MIRAI-ASRC, AIST), Masashi Takahashi (MIRAI-ASET), Hiroyuki Ota (MIRAI-ASRC, AIST), Toshihide Nabatame (MIRAI-ASET), Akira Toriumi (The University of Tokyo) SDM2008-51
 [more] SDM2008-51
SDM 2006-06-22
Hiroshima Faculty Club, Hiroshima Univ. unknown
Wataru Mizubayashi (MIRAI-ASRC, AIST), Arito Ogawa, Toshihide Nabatame, Hideki Satake (MIRAI-ASET), Akira Toriumi (MIRAI-ASRC, AIST, Univ. of Tokyo)
 [more] SDM2006-61
 Results 1 - 15 of 15  /   
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