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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-27
08:50
Kagoshima   Automatic distortion compensation technique in resistor ladder for high-speed and low-power ADC
Wataru Yoshimura, Kenichi Ohhata (Kagoshima Univ.) CPM2013-108 ICD2013-85
A resistor ladder is an important circuit block for the parallel architecture analog-to-digital converters (ADCs). The o... [more] CPM2013-108 ICD2013-85
pp.1-6
ICD, ITE-IST 2013-07-05
15:25
Hokkaido San Refre Hakodate 1-GHz, 8-bit Subranging ADC(1) -- Low-power techniques --
Masataro Iwamoto, Wataru Yoshimura, Futoshi Shimozono, Daiki Tabira, Kenichi Ohhata (Kagoshima Univ.) ICD2013-40
An AD converter architecture combining a capacitive DAC and a built-in Vth technology was proposed to reduce the power c... [more] ICD2013-40
pp.101-106
ICD, ITE-IST 2013-07-05
15:50
Hokkaido San Refre Hakodate 1-GHz, 8-bit Subranging ADC(2) -- Experimental results and failure analysis --
Wataru Yoshimura, Masataro Iwamoto, Futoshi Shimozono, Daiki Tabira, Kenichi Ohhata (Kagoshima Univ.) ICD2013-41
An 8-bit subranging AD converter was fabricated by 65-nm CMOS technology featuring an ultra-low-power AD converter archi... [more] ICD2013-41
pp.107-112
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