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 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-28
10:25		 Kagoshima   Development of a fine-grain power-gated CPU "Geyser-3" and adaptive power-off control to the temperature
Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui (Shibaura Inst. of Tech.), Weihan Wang, Hideharu Amano (Keio Univ), Ryuichi Sakamoto, Mitaro Namiki (Tokyo Univ of Agriculture and Tech), Masaaki Kondo (Univ of Elec-Comm), Hiroshi Nakamura (Univ of Tokyo) VLD2013-80 DC2013-46		  [more] VLD2013-80 DC2013-46
pp.135-140
RECONF 2013-09-19
09:00		 Ishikawa Japan Advanced Institute of Science and Technology A Low power Reconfigurable Accelerator using a Back-gate Bias Control Technique
Hongliang Su, Weihan Wang, Hideharu Amano (Keio Univ.) RECONF2013-26		 Leakage power is a serious problem especially for accerelators which use a large size Processing Ele- ment (PE) array. H... [more] RECONF2013-26
pp.37-42
CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] 2013-03-14
08:45		 Nagasaki   Power optimization of micro-controller with Sillicon on Thin Buried Oxide
Kuniaki Kitamori, Weihan Wang, Hongliang Su, Hideharu Amano (Keio Univ.) CPSY2012-85 DC2012-91		 Nowadays, from battery supplied mobile devices to supercomputers, reducing the power consumption has become a serious de... [more] CPSY2012-85 DC2012-91
pp.199-204
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2012-11-27
13:50		 Fukuoka Centennial Hall Kyushu University School of Medicine Low Power Reconfiguarable Accelerator Design with Silicon on Thin Buried Oxide
Hongliang Su, Weihan Wang, Hideharu Amano (Keio Univ.) RECONF2012-47		 Nowadays，with the development of low power supply voltage Vdd，it is becoming a serious issue that the bios of threshold ... [more] RECONF2012-47
pp.3-8
CPSY 2011-10-21
09:50		 Hyogo   Study of Mixed Power Gating on VLIW Processors
Yoshifumi Ishii, Weihan Wang, Hideharu Amano (Keio Univ.) CPSY2011-26		 Power Gating (PG) is an effective way to reduce leakage power that becomes a big issue in LSI designs. There are two way... [more] CPSY2011-26
pp.7-12
DC, CPSY
(Joint)		 2011-07-29
09:00		 Kagoshima   Reducing Leakage Power Consumption of Functional Units with Fine-grained Power Gating
Weihan Wang (Keio Univ.), Yuya Ohta (Shibaura inst. of tech.), Lei Zhao (Keio Univ.), Yoshifumi Ishii (Keio univ.), Kimiyoshi Usami (Shibaura inst. of tech.), Hideharu Amano (Keio Univ.) CPSY2011-9		 High speed power gating techniques are useful for reducing leakage power by functional units of CPU core. This paper pre... [more] CPSY2011-9
pp.1-6
 Results 1 - 6 of 6  /   
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