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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM, ICD, ITE-IST [detail] | 2023-08-02 09:00 |
Hokkaido | Hokkaido Univ. Multimedia Education Bldg. 3F (Primary: On-site, Secondary: Online) |
[Invited Talk]
A 33kDMIPS 6.4W Vehicle Communication Gateway Processor Achieving 10Gbps/W Network Routing, 40ms CAN Bus Start-Up and 1.4mW Standby Kenichi Shimada, Keiichiro Sano, Kazuki Fukuoka, Hiroshi Morita, Masayuki Daito, Tatsuya Kamei, Hiroyuki Hamasaki, Yasuhisa Shimazaki (Renesas)  SDM2023-43 ICD2023-22 |
[more] | SDM2023-43 ICD2023-22 pp.36-40 |
| SDM, ICD, ITE-IST [detail] | 2019-08-09 10:50 |
Hokkaido | Hokkaido Univ., Graduate School /Faculty of Information Science and | [Invited Talk]
A 28nm 600MHz Automotive Flash Microcontroller with Virtualization-Assisted Processor for Next-Generation Automotive Architecture supporting ISO26262 ASIL-D Naoto Okumura, Sugako Otani, Norimasa Otsuki, Yasufumi Suzuki, Shohei Maeda, Tomonori Yanagita, Takao Koike, Masao Ito, Minoru Uemura, Yasuhisa Shimazaki, Toshihiro Hattori, Noriaki Sakamoto, Hiroyuki Kondo (Renesas Electronics Corp.) SDM2019-47 ICD2019-12 |
Along with the rapid progress of automotive Electrical/Electronic(E/E) architecture, further integration of multiple ele... [more] | SDM2019-47 ICD2019-12 pp.67-71 |
| ICD, SDM, ITE-IST [detail] | 2016-08-03 13:20 |
Osaka | Central Electric Club | [Invited Talk]
A 16nm FinFET Heterogeneous Nona-Core SoC Supporting Functional Safety Standard ISO26262 ASIL B Chikafumi Takahashi, Shinichi Shibahara, Kazuki Fukuoka, Jun Matsushima, Yuko Kitaji (Renesas System Design), Yasuhisa Shimazaki, Hirotaka Hara, Takahiro Irita (Renesas Electronics) SDM2016-64 ICD2016-32 |
This paper presents an SoC for the next generation of car infotainment, achieving high performance powered by nine heter... [more] | SDM2016-64 ICD2016-32 pp.105-110 |
| ICD | 2013-04-12 15:30 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | [Invited Lecture]
Reduction of SRAM Standby Leakage utlizing All Digital Current Comparator Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yasuhisa Shimazaki (Renesas Electronics) ICD2013-21 |
A high-performance and low-leakage current embedded SRAM for mobile phones is proposed. The proposed SRAM has two low-vo... [more] | ICD2013-21 pp.109-114 |
| ICD | 2012-04-24 11:15 |
Iwate | Seion-so, Tsunagi Hot Spring (Iwate) | [Invited Talk]
Write-/Read- Disturb Issues and Circuit Solutions Yuichiro Ishii, Yasumasa Tsukamoto, Koji Nii, Hidehiro Fujiwara, Makoto Yabuuchi, Koji Tanaka, Shinji Tanaka, Yasuhisa Shimazaki (Renesas Electronics) ICD2012-11 |
This paper describes some circuit techniques for an 8T dual-port (DP) SRAM to improve its minimum operating voltage agai... [more] | ICD2012-11 pp.55-60 |
| VLD, IPSJ-SLDM | 2010-05-20 10:00 |
Fukuoka | Kitakyushu International Conference Center | 3D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link Makoto Saen, Kenichi Osada, Yasuyuki Okuma (Hitachi), Yasuhisa Shimazaki (Keio Univ./Renesas Technology), Itaru Nonomura (Renesas Technology), Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Tadahiro Kuroda (Keio Univ.) VLD2010-5 |
This paper describes a three-dimensional (3D) system integration of a fully functional processor chip and two memory chi... [more] | VLD2010-5 pp.43-47 |
| ICD | 2010-04-22 11:15 |
Kanagawa | Shonan Institute of Tech. | A 40-nm Low-power SRAM with Multi-stage Replica-Bitline Scheme for Reducing Timing Variation Shigenobu Komatsu, Masanao Yamaoka (HITACHI), Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki (Renesas Technology Corp.), Kenichi Osada (HITACHI) ICD2010-4 |
A multi-stage replica bitline scheme for reducing access time by suppressing enable timing variation of a sense amplifie... [more] | ICD2010-4 pp.17-21 |
| ICD | 2009-12-15 17:00 |
Shizuoka | Shizuoka University (Hamamatsu) | A 3D Processor Using Inductive-Coupling Inter-Chip Link
-- 3D System Integration of a 90nm CMOS Processor and a 65nm CMOS SRAM -- Kiichi Niitsu (Keio Univ./JST), Yasuhisa Shimazaki (Keio Univ./Renesas Technology), Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga (Keio Univ.), Itaru Nonomura (Renesas Technology), Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko Irie (Hitachi), Toshihiro Hattori, Atsushi Hasegawa (Renesas Technology), Tadahiro Kuroda (Keio Univ.) ICD2009-105 |
A 90nm CMOS processor is mounted face down on a package by C4 bump and a 65nm CMOS 1MB SRAM is glued on it face up. The ... [more] | ICD2009-105 pp.163-168 |
| ICD | 2008-04-17 10:15 |
Tokyo | [Invited Talk]
65nm Low-Power High-Density SRAM Operable at 1.0V under 3sigma Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS Masanao Yamaoka (Hitachi, Ltd.), Noriaki Maeda, Yasuhisa Shimazaki (Renesas), Kenichi Osada (Hitachi, Ltd.) ICD2008-2 |
A 1Mb SRAM is fabricated in 65nm LP process with 0.51μm2 cell. An NMOS and PMOS separately applied body bias technique a... [more] | ICD2008-2 pp.7-12 |
|
| ICD | 2006-05-25 13:30 |
Hyogo | Kobe University | Hierarchical Power Distribution with dozens of power domain in 90-nm Low-power SoCs Yusuke Kanno (HCRL), Hiroyuki Mizuno (Hitachi), Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi (Renesas), Toshifumi Ishii (Hitachi ULSI), Tetsuya Yamada (HCRL), Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa (Renesas), Naohiko Irie (HCRL) |
[more] | ICD2006-26 pp.25-30 |
| ICD | 2005-04-14 09:30 |
Fukuoka | Low-Power Embedded SRAM Modules with Expanded Margins for Writing Masanao Yamaoka (Hitachi, Ltd.), Noriaki Maeda (Renesas), Yoshihiro Shinozaki (Hitachi ULSI), Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa (Renesas), Takayuki Kawahara (Hitachi, Ltd.) |
The power consumption of a low-power SoC has a battery life of mobile appliances. The general SoCs have large on-chip SR... [more] | ICD2005-2 pp.7-12 |
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