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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
NC, MBE (Joint) |
2023-10-28 10:45 |
Miyagi |
Tohoku Univ. (Primary: On-site, Secondary: Online) |
A design of ultra-low power reservoir computing system with analog CMOS spiking neural network circuits Satoshi Ono, Satoshi Moriya, Hideaki Yamamoto (Tohoku Univ.), Yasushi Yuminaka (Gunma Univ.), Yoshihiko Horio, Shigeo Sato (Tohoku Univ.) NC2023-29 |
Spiking neural network (SNN) is expected to be applied to edge computing due to its low power consumption when implement... [more] |
NC2023-29 p.23 |
NC, MBE (Joint) |
2022-09-29 10:25 |
Miyagi |
Tohoku Univ. (Primary: On-site, Secondary: Online) |
Analog circuit implementation of spiking neural networks and its application to time-series information processing Satoshi Moriya, Hideaki Yamamoto (Tohoku Univ), Yasushi Yuminaka (Gunma Univ.), Shigeo Sato, Yoshihiko Horio (Tohoku Univ) NC2022-33 |
Edge computing in which low-dimensional signals such as sensor output are processed nearby sensors have become increasin... [more] |
NC2022-33 p.5 |
NC, IBISML, IPSJ-BIO, IPSJ-MPS [detail] |
2022-06-29 14:20 |
Okinawa |
(Primary: On-site, Secondary: Online) |
LSI implementation of analog CMOS majority circuit for neural network applications Satoshi Ono, Satoshi Moriya, Yuka Kanke, Hideaki Yamamoto (Tohoku Univ.), Yasushi Yuminaka (Gunma Univ.), Shigeo Sato (Tohoku Univ.) NC2022-27 IBISML2022-27 |
Majority logic circuit is a circuit whose output is the majority value of multiple binary inputs. It can be applied to b... [more] |
NC2022-27 IBISML2022-27 pp.189-192 |
NLP, MICT, MBE, NC (Joint) [detail] |
2022-01-23 09:50 |
Online |
Online |
Analog-circuit design of STDP learning rule with linear decay and its LSI implementation Satoshi Moriya, Tatsuki Kato (Tohoku Univ.), Yasushi Yuminaka (Gunma Univ.), Hideaki Yamamoto, Shigeo Sato, Yoshihiko Horio (Tohoku Univ.) NC2021-40 |
Spiking neural networks (SNNs) are expected to be the next generation of information processing technology to reduce the... [more] |
NC2021-40 p.44 |
NLP, MICT, MBE, NC (Joint) [detail] |
2022-01-23 10:15 |
Online |
Online |
Analog CMOS implementation of majority logic for neuromorphic circuit applications Satoshi Ono, Satoshi Moriya, Yuka Kanke, Hideaki Yamamoto (Tohoku Univ.), Yasushi Yuminaka (Gunma Univ.), Shigeo Sato (Tohoku Univ.) NC2021-41 |
A majority logic circuit is a circuit whose output is the majority value of multiple binary inputs. In addition to its c... [more] |
NC2021-41 pp.45-48 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-08 09:25 |
Kumamoto |
Kumamoto-Kenminkouryukan Parea |
Real-time coefficient optimization method for PAM-4 transmitter equalizer Yosuke Iijima, Keigo Taya (NIT, Oyama college), Yasushi Yuminaka (Gunma Univ.) VLD2017-56 DC2017-62 |
Recently, demands for high-speed data transmission in electric wiring in a VLSI system are increasing with the advanceme... [more] |
VLD2017-56 DC2017-62 pp.177-182 |
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