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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD 2014-04-18
09:30
Tokyo Kikai-Shinko-Kaikan Bldg. A 0.38-V Operating STT-MRAM with Process Variation Tolerant Sense Amplifier
Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.), Koji Tsunoda, Toshihiro Sugii (LEAP) ICD2014-10
This paper exhibits a 65-nm 8-Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at a s... [more] ICD2014-10
pp.47-51
ICD 2014-01-28
15:00
Kyoto Kyoto Univ. Tokeidai Kinenkan [Poster Presentation] STT-MRAM Architecture for Improving Throughput
Haruki Mori, Koji Yanagida, Yohei Umeki, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.), Koji Tsunoda, Toshihiro Sugii (LEAP) ICD2013-110
STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory) attracts an attention as the substitute memory of SRAM. Th... [more] ICD2013-110
p.27
ICD 2012-12-17
15:55
Tokyo Tokyo Tech Front [Poster Presentation] Low-Power Ferroelectric 6T4C Shadow SRAM for Normally-Off Computing
Tomoki Nakagawa, Shusuke Yoshimoto, Yuki Kitahara, Koji Yanagida, Yohei Umeki, Shunsuke Okumura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2012-98
In recent years, sensor network has attracted much attention in agricultural, medical, and disaster-prevention area to c... [more] ICD2012-98
p.41
ICD, SDM 2012-08-02
09:35
Hokkaido Sapporo Center for Gender Equality, Sapporo, Hokkaido A 40-nm 256-Kb Sub-10 pJ/Access 8T SRAM with Read Bitline Amplitude Limiting (RBAL) Scheme
Shusuke Yoshimoto, Masaharu Terada, Yohei Umeki, Shunsuke Okumura (Kobe Univ.), Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano (STARC), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) SDM2012-64 ICD2012-32
 [more] SDM2012-64 ICD2012-32
pp.7-12
ICD 2012-04-24
15:15
Iwate Seion-so, Tsunagi Hot Spring (Iwate) Low-Energy Block-Level Instantaneous Comparison 7T SRAM for Dual Modular Redundancy
Yohei Umeki, Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST) ICD2012-16
This paper proposes a 7T SRAM that realizes a block-level instantaneous comparison feature. The proposed SRAM is useful ... [more] ICD2012-16
pp.85-90
ICD 2011-12-16
14:50
Osaka   Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure
Yohei Umeki, Shusuke Yoshimoto, Takurou Amashita, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST) ICD2011-134
This paper presents a new 8T (8-transistor) SRAM cell layout mitigating multiple-bit upset (MBU) in a divided wordline s... [more] ICD2011-134
pp.161-166
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