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Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS, VLD [detail] 2021-03-03
Online Online [Memorial Lecture] Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization
TaiYu Cheng (Osaka Univ.), Yutaka Masuda (Nagoya Univ.), Jun Nagayama, Yoichi Momiyama (Socionext Inc.), Jun Chen, Masanori Hashimoto (Osaka Univ.) VLD2020-72 HWS2020-47
This paper proposes a design optimization methodology that can achieve a mode-wise voltage scalable (MWVS) design with a... [more] VLD2020-72 HWS2020-47
ICD, SDM 2009-07-16
Tokyo Tokyo Institute of Technology Comprehensive Design Methodology of Dopant Profile to Suppress Gate-LER-induced Threshold Voltage Variability in sub-30 nm NMOSFETs
Hidenobu Fukutome (Fujitsu Microelectronics Limited), Yoko Hori (Fujitsu Quality Lab. Limited), Kimihiko Hosaka, Yoichi Momiyama, Shigeo Satoh, Toshihiro Sugii (Fujitsu Microelectronics Limited) SDM2009-106 ICD2009-22
We have demonstrated for the first time that parallel extension implantation tilted along the gate width direction enabl... [more] SDM2009-106 ICD2009-22
ICD, SDM 2008-07-18
Tokyo Kikai-Shinko-Kaikan Bldg. High Performance Sub-35 nm Bulk CMOS with Hybrid Gate Structures of NMOS; Dopant Confinement Layer (DCL) / PMOS; Ni-FUSI by Using Flash Lamp Anneal (FLA) in Ni-Silicidation -- Hybrid Gate Structures --
Hiroyuki Ohta (Fujitsu Lab.), Kazuo Kawamura (FML), Hidenobu Fukutome (Fujitsu Lab.), Mitsugu Tajima, Ken-ichi Okabe (FML), Keiji Ikeda, Kimihiko Hosaka, Yoichi Momiyama, Shigeo Satoh, Toshihiro Sugii (Fujitsu Lab.) SDM2008-148 ICD2008-58
We applied Flash Lamp Annealing (FLA) in Ni-silicidation to our developed Dopant Confinement Layer (DCL) structure for t... [more] SDM2008-148 ICD2008-58
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