IEICE Technical Committee Submission System
Conference Schedule		 Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 1 of 1  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, SDM 2009-07-16
15:25		 Tokyo Tokyo Institute of Technology Comprehensive Design Methodology of Dopant Profile to Suppress Gate-LER-induced Threshold Voltage Variability in sub-30 nm NMOSFETs
Hidenobu Fukutome (Fujitsu Microelectronics Limited), Yoko Hori (Fujitsu Quality Lab. Limited), Kimihiko Hosaka, Yoichi Momiyama, Shigeo Satoh, Toshihiro Sugii (Fujitsu Microelectronics Limited) SDM2009-106 ICD2009-22		 We have demonstrated for the first time that parallel extension implantation tilted along the gate width direction enabl... [more] SDM2009-106 ICD2009-22
pp.49-52
 Results 1 - 1 of 1  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan